Xilinx Virtex-6 Manual page 214

Chapter 4: About Design Elements
Inputs
I3 I2
1 1
1 1
1 1
1 1
INIT = Binary equivalent of the hexadecimal number assigned to the INIT attribute
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
Available Attributes
Attribute Data Type
INIT Hexadecimal
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- LUT4: 4-input Look-Up Table with general output
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
LUT4_inst : LUT4
generic map (
INIT => X"0000")
port map (
O => O, -- LUT general output
I0 => I0, -- LUT input
I1 => I1, -- LUT input
I2 => I2, -- LUT input
I3 => I3 -- LUT input
);
-- End of LUT4_inst instantiation
214
I1 I0
0 0
0 1
1 0
1 1
Yes
Recommended
No
No
Allowed Values Default
Any 16-Bit Value All zeros
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Outputs
O
INIT[12]
INIT[13]
INIT[14]
INIT[15]
Description
Initializes look-up tables.
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013