Xilinx Virtex-6 Manual page 193

LDPE
Primitive: Transparent Data Latch with Asynchronous Preset and Gate Enable
Introduction
This design element is a transparent data latch with asynchronous preset and gate enable. When the
asynchronous preset (PRE) is High, it overrides the other input and presets the data (Q) output High. Q reflects
the data (D) input while the gate (G) input and gate enable (GE) are High. The data on the (D) input during the
High-to-Low gate transition is stored in the latch. The data on the (Q) output remains unchanged as long as
(G) or (GE) remains Low.
The latch is asynchronously preset, output High, when power is applied. For FPGA devices, power-on conditions
are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an
inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic Table
Inputs
PRE GE
1 X
0 0
0 1
0 1
0 1
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
Available Attributes
Attribute Data Type
INIT Binary
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
G
X
X
1
0
↓
Allowed Values Default
0, 1 1
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Chapter 4: About Design Elements
D
X
X
D
X
D
Yes
Recommended
No
No
Description
Specifies the initial value upon power-up or the
assertion of GSR for the (Q) port.
Outputs
Q
1
No Change
D
No Change
D
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