Xilinx Virtex-6 Manual page 62

Chapter 2: About Unimacros
FIFO_SYNC_MACRO
Macro: Synchronous First-In, First-Out (FIFO) RAM Buffer
Introduction
FPGA devices contain several block RAM memories that can be configured as general-purpose 36kb or 18kb
RAM/ROM memories. Dedicated logic in the block RAM enables you to easily implement FIFOs. The FIFO
can be configured as an 18 kb or 36 kb memory. This unimacro configures the FIFO such that it uses one clock
for reading as well as writing.
Port Description
Name
Output Ports
ALMOSTEMPTY
ALMOSTFULL
DO
EMPTY
FULL
RDCOUNT
RDERR
WRCOUNT
WRERR
62
Direction Width
Output 1
Output 1
Output See Configuration
Table.
1
Output
Output 1
Output
See Configuration
Table below.
Output 1
Output See Configuration
Table.
Output 1
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Function
Almost all valid entries in FIFO have been read.
Almost all entries in FIFO memory have been
filled.
Data output bus addressed by ADDR.
FIFO is empty.
All entries in FIFO memory are filled.
FIFO data read pointer.
When the FIFO is empty, any additional read
operation generates an error flag.
FIFO data write pointer.
When the FIFO is full, any additional write
operation generates an error flag.
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013