Xilinx Virtex-6 Manual page 6

Chapter 2: About Unimacros
BRAM_SDP_MACRO
Macro: Simple Dual Port RAM
Introduction
FPGA devices contain several block RAM memories that can be configured as general-purpose 36Kb or 18Kb
RAM/ROM memories. These block RAM memories offer fast and flexible storage of large amounts of on-chip
data. Both read and write operations are fully synchronous to the supplied clock(s) of the component. However,
read and write ports can operate fully independently and asynchronously to each other, accessing the same
memory array. Byte-enable write operations are possible, and an optional output register can be used to reduce
the clock-to-out times of the RAM.
Note This element, must be configured so that read and write ports have the same width.
Port Description
Name Direction
Output Ports
DO Output
Input Ports
DI Input
Input
WRADDR,
RDADDR
WE Input
6
Width (Bits)
See Configuration Table
See Configuration Table
See Configuration Table
See Configuration Table
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Function
Data output bus addressed by RDADDR.
Data input bus addressed by WRADDR.
Write/Read address input buses.
Byte-Wide Write enable.
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013