Xilinx Virtex-6 Manual page 316

Chapter 4: About Design Elements
Verilog Instantiation Template
// RAM64M: 64-deep by 4-wide Multi Port LUT RAM
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
RAM64M #(
.INIT_A(64'h0000000000000000), // Initial contents of A Port
.INIT_B(64'h0000000000000000), // Initial contents of B Port
.INIT_C(64'h0000000000000000), // Initial contents of C Port
.INIT_D(64'h0000000000000000)
) RAM64M_inst (
.DOA(DOA), // Read port A 1-bit output
.DOB(DOB), // Read port B 1-bit output
.DOC(DOC), // Read port C 1-bit output
.DOD(DOD), // Readw/rite port D 1-bit output
.DIA(DIA), // RAM 1-bit data write input addressed by ADDRD,
// read addressed by ADDRA
.DIB(DIB), // RAM 1-bit data write input addressed by ADDRD,
// read addressed by ADDRB
.DIC(DIC), // RAM 1-bit data write input addressed by ADDRD,
// read addressed by ADDRC
.DID(DID), // RAM 1-bit data write input addressed by ADDRD,
// read addressed by ADDRD
.ADDRA(ADDRA), // Read port A 6-bit address input
.ADDRB(ADDRB), // Read port B 6-bit address input
.ADDRC(ADDRC), // Read port C 6-bit address input
.ADDRD(ADDRD), // Readw/rite port D 6-bit address input
.WE(WE), // Write enable input
.WCLK(WCLK) // Write clock input
);
// End of RAM64M_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
316
// Initial contents of D Port
www.xilinx.com
Sheets).
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013