Xilinx Virtex-6 Manual page 359

SIM_CONFIG_V6_SERIAL
Simulation: Serial Configuration Simulation Model
Introduction
This simulation component allows the functional simulation of many of the common serial configuration
interface, functions and commands to assist with board-level understanding and debug of configuration
behaviors. The model can also simulate some startup-up behaviors such as the global set/reset (GSR) and global
3-state (GTS) assertion in the design. This model does not map to a specific primitive in the FPGA software and
cannot be directly instantiated in the design, however it can be used in conjunction with the source design if
specified either in a simulation-only file like a testbench or by some means guarded from synthesis so that it is
not synthesized into the design netlist. This model may be used for either functional (RTL) simulation or
timing simulation.
Port Descriptions
Port Direction
DONE Inout
DOUT Output
CCLK Input
DIN Input
INITB Input
M Input
PROGB Input
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Width Function
1
Active-High signal indicating configuration is complete:
• 0 = FPGA not configured
• 1 = FPGA configured
1
Serial data output for downstream daisy-chained devices. Data
provided on the falling edge of CCLK.
1 Configuration clock source for all configuration modes except JTAG.
1 Serial configuration data input, synchronous to rising CCLK edge.
1 Before the Mode pins are sampled, INIT_B is an input that can be
held Low to delay configuration. After the Mode pins are sampled,
INIT_B is an open-drain, active-Low output indicating whether a
CRC error occurred during configuration:
• 0 = CRC error
• 1 = No CRC error
When the SEU detection function is enabled, INIT_B is optionally
driven Low when a read back CRC error is detected.
2 Mode pins - determine configuration mode.
1 Active-Low asynchronous full-chip reset.
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Chapter 4: About Design Elements
359