Xilinx Virtex-6 Manual page 339

Attribute
WRITE_WIDTH_A
WRITE_WIDTH_B
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- RAMB36E1: 36K-bit Configurable Synchronous Block RAM
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
RAMB36E1_inst : RAMB36E1
generic map (
-- Colision check: Values ("ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE")
SIM_COLLISION_CHECK => "ALL",
-- DOA_REG, DOB_REG: Optional output register (0 or 1)
DOA_REG => 0,
DOB_REG => 0,
-- Error Correction Circuitry (ECC): Encoder/decoder enable (TRUE/FALSE)
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
-- INITP_00 to INITP_0F: Initial contents of the parity memory array
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- INIT_00 to INIT_7F: Initial contents of the data memory array
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Data Type Allowed Values
Integer 0, 1, 2, 4, 9, 18, 36
Integer 0, 1, 2, 4, 9, 18, 36, 72
www.xilinx.com
Chapter 4: About Design Elements
Default Description
0 Specifies the desired data width for a
write on port A, including parity bits.
This value must be 0 if the port is not
used. Otherwise, it should be set to the
desired port width.
0 Specifies the desired data width for a
write on port B, including parity bits.
This value must be 0 if the port is not
used. Otherwise, it should be set to the
desired port width.
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