Xilinx Virtex-6 Manual page 301

Port Direction
ADDRB Input
ADDRC Input
ADDRD Input
WE Input
WCLK Input
Design Entry Method
Instantiation
Inference
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This element can be inferred by some synthesis tools by describing a RAM with a synchronous write and
asynchronous read capability. Consult your synthesis tool documentation for details on RAM inference
capabilities and coding examples. Xilinx suggests that you instantiate RAM32Ms if you have a need to implicitly
specify the RAM function, or if you need to manually place or relationally place the component. If a synchronous
read capability is desired, the RAM32M outputs can be connected to an FDRSE (FDCPE is asynchronous set/reset
is necessary) in order to improve the output timing of the function. However, this is not necessary for the
proper operation of the RAM.
If you want to have the data clocked on the negative edge of a clock, an inverter can be described on the clock
input to this component. This inverter will be absorbed into the block, giving you the ability to write to the RAM
on falling clock edges.
If instantiated, the following connections should be made to this component. Tie the WCLK input to the desired
clock source, the DIA, DIB, DIC and DID inputs to the data source to be stored and the DOA, DOB, DOC and
DOD outputs to an FDCE D input or other appropriate data destination or left unconnected if not used. The WE
clock enable pin should be connected to the proper write enable source in the design. The 5-bit ADDRD bus
should be connected to the source for the read/write addressing and the 5-bit ADDRA, ADDRB and ADDRC
buses should be connected to the appropriate read address connections. The optional INIT_A, INIT_B, INIT_C
and INIT_D attributes consisting of a 64-bit hexadecimal values that specifies each port's initial memory contents
can be specified. The INIT value correlates to the RAM addressing by the following equation: ADDRy[z] =
INIT_y[2*z+1:2*z]. For instance, if the RAM ADDRC port is addressed to 00001, then the INIT_C[3:2] values
would be the initial values shown on the DOC port before the first write occurs at that address. If left unspecified,
the initial contents will default to all zeros.
Available Attributes
Attribute Data Type
INIT_A Hexadecimal
INIT_B
Hexadecimal
INIT_C Hexadecimal
INIT_D Hexadecimal
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Width Function
5
Read address bus B
5
Read address bus C
5
8-bit data write port, 2-bit data read port address bus D
1 Write Enable
1 Write clock (reads are asynchronous)
Yes
Recommended
No
No
Allowed Values Default
Any 64-Bit Value All zeros
Any 64-Bit Value All zeros
Any 64-Bit Value All zeros
Any 64-Bit Value All zeros
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Chapter 4: About Design Elements
Description
Specifies the initial contents of the RAM on
the A port.
Specifies the initial contents of the RAM on
the B port.
Specifies the initial contents of the RAM on
the C port.
Specifies the initial contents of the RAM on
the D port.
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