Xilinx Virtex-6 Manual page 149

IBUFDS
Primitive: Differential Signaling Input Buffer
Introduction
This design element is an input buffer that supports low-voltage, differential signaling. In IBUFDS, a design
level interface signal is represented as two distinct ports (I and IB), one deemed the "master" and the other the
"slave." The master and the slave are opposite phases of the same logical signal (for example, MYNET_P and
MYNET_N). Optionally, a programmable differential termination feature is available to help improve signal
integrity and reduce external components.
Logic Table
Inputs
I
0
0
1
1
Port Descriptions
Port
I
IB
O
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
Put all I/O components on the top-level of the design to help facilitate hierarchical design methods. Connect
the I port directly to the top-level "master" input port of the design, the IB port to the top-level "slave" input
port, and the O port to the logic in which this input is to source. Specify the desired generic/defparam values in
order to configure the proper behavior of the buffer.
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
IB
0
1
0
1
Direction
Input
Input
Output
www.xilinx.com
Chapter 4: About Design Elements
Outputs
O
No Change
0
1
No Change
Width
1
1
1
Recommended
No
No
No
Function
Diff_p Buffer Input
Diff_n Buffer Input
Buffer Output
149