Xilinx Virtex-6 Manual page 8

Chapter 2: About Unimacros
Available Attributes
Attribute Data Type
BRAM_SIZE String
DO_REG Integer
INIT Hexadecimal
READ_WIDTH, Integer
WRITE_WIDTH
INIT_FILE
String
SIM_COLLISION_ String
CHECK
8
Allowed Values Default
"36Kb", "18Kb" "18Kb"
0, 1 0
Any 72-Bit Value All zeros
1-72 36
None
String representing
file name and
location
"ALL", "ALL"
"WARNING_
ONLY",
"GENERATE_X_
ONLY",
"NONE"
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Description
Configures RAM as "36Kb" or "18Kb"
memory.
A value of 1 enables to the output
registers to the RAM enabling quicker
clock-to-out from the RAM at the
expense of an added clock cycle of
read latency. A value of 0 allows a
read in one clock cycle but will have
slower clock to out timing.
Specifies the initial value on the
output after configuration.
Specifies the size of the DI and DO
buses.
The following combinations are
allowed:
• READ_WIDTH =
WRITE_WIDTH
• If asymmetric, READ_WIDTH
and WRITE_WIDTH must be in
the ratio of 2, or must be values
allowed by the unisim (1, 2, 4, 8,
9, 16, 18, 32, 36, 64, 72)
Name of the file containing initial
values.
Allows modification of the simulation
behavior if a memory collision occurs.
The output is affected as follows:
• "ALL" - Warning produced
and affected outputs/memory
location go unknown (X).
• "WARNING_ONLY" - Warning
produced and affected
outputs/memory retain last
value.
• "GENERATE_X_ONLY" - No
warning. However, affected
outputs/memory go unknown
(X).
• "NONE" - No warning and
affected outputs/memory retain
last value.
Note Setting this to a value other
than "ALL" can allow problems in
the design go unnoticed during
simulation. Care should be taken
when changing the value of this
attribute. Please see the Synthesis
and Simulation Design Guide for more
information.
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013