Xilinx Virtex-6 Manual page 147

IBUF
Primitive: Input Buffer
Introduction
This design element is automatically inserted (inferred) by the synthesis tool to any signal directly connected
to a top-level input or in-out port of the design. You should generally let the synthesis tool infer this buffer.
However, it can be instantiated into the design if required. In order to do so, connect the input port (I) directly to
the associated top-level input or in-out port, and connect the output port (O) to the logic sourced by that port.
Modify any necessary generic maps (VHDL) or named parameter value assignment (Verilog) in order to change
the default behavior of the component.
Port Descriptions
Port Direction
O Output
I Input
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
This element is usually inferred by the synthesis tool for any specified top-level input port to the design, and
therefore it is generally not necessary to specify the element in source code. However, if desired, this element
may be manually instantiated by copying the instantiation code from below and pasting it into the top-level
entity/module of your code. Xilinx recommends that you put all I/O components on the top-level of the design to
help facilitate hierarchical design methods. Connect the I port directly to the top-level input port of the design
and the O port to the logic in which this input is to source. Specify the desired generic/defparam values in
order to configure the proper behavior of the buffer.
Available Attributes
Attribute Data Type
IOSTANDARD String
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Width
1
1
Yes
Recommended
No
No
Allowed Values Default
See Data Sheet. "DEFAULT"
www.xilinx.com
Chapter 4: About Design Elements
Function
Buffer output
Buffer input
Description
Assigns an I/O standard to the element.
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