Xilinx Virtex-6 Manual page 136

Chapter 4: About Design Elements
Port
DI[63:0]
DIP[7:0]
DO[63:0]
DOP[7:0]
ECCPARITY[7:0]
EMPTY
FULL
INJECTDBITERR
INJECTSBITERR
RDEN
REGCE
RST
RSTREG
SBITERR
WRCLK, RDCLK
WRCOUNT,
RDCOUNT
WREN
WRERR,
RDERR
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
136
Direction Width
Input 64
Input 8
Output 64
Output 8
Output 8
Output 1
1
Output
Input 1
Input 1
Input 1
Input 1
Input 1
Input 1
Output 1
Input 1
Output 13
Input 1
Output 1
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Function
FIFO data input bus.
FIFO parity data input bus.
FIFO data output bus.
FIFO parity data output bus.
8-bit data generated by the ECC encoder used by
the ECC decoder for memory error detection and
correction.
Active high logic to indicate that the FIFO is currently
empty.
Active high logic indicates that the FIFO is full.
Inject a double bit error if ECC feature is used.
Inject a single bit error if ECC feature is used.
Active high FIFO read enable.
Output register clock enable for pipelined synchronous
FIFO.
Active high (FIFO logic) asynchronous reset (for
dual-clock FIFO), synchronous reset (synchronous
FIFO) for 3 CLK cycles.
Output register synchronous set/reset.
Status output from ECC function to indicate a single bit
error was detected. EN_ECC_READ needs to be TRUE
in order to use this functionality.
FIFO read and write clocks (positive edge triggered).
FIFO write/read pointer.
Active high FIFO write enable.
• WRERR indicates that a write occurred while the
FIFO was full.
• RDERR indicates that a read occurred while the
FIFO was empty.
Yes
No
No
Recommended
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013