Xilinx Virtex-6 Manual page 180

Chapter 4: About Design Elements
ISERDESE1
Primitive: Input SERial/DESerializer
Introduction
This design element is a dedicated serial-to-parallel converter with specific clocking and logic features designed
to facilitate the implementation of high-speed source-synchronous applications. It avoids the additional timing
complexities encountered when designing deserializers in the FPGA fabric.
Port Descriptions
Port
BITSLIP
CE1
CE2
CLK
CLKB
180
Direction Width Function
Input 1
The BITSLIP pin performs a Bitslip operation synchronous to
CLKDIV when asserted (active High). Subsequently, the data
seen on the Q1 to Q6 output ports will shift, as in a barrel-shifter
operation, one position every time Bitslip is invoked (DDR
operation is different from SDR).
Input 1 Data register clock enable.
Input 1 Data register clock enable.
Input 1 Primary clock input pin used.
Input 1 The high-speed secondary clock input (CLKB) is used to
clock in the input serial data stream. In any mode other than
MEMORY_QDR, connect CLKB to an inverted version of CLK. In
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Virtex-6 Libraries Guide for HDL Designs
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