Xilinx Virtex-6 Manual page 283

Chapter 4: About Design Elements
OSERDESE1
Primitive: Dedicated IOB Output Serializer
Introduction
This design element is a dedicated parallel-to-serial converter with specific clocking and logic resources designed
to facilitate the implementation of high-speed source-synchronous interfaces. Every OSERDES module includes
a dedicated serializer for data and 3-state control. Both data and 3-state serializers can be configured in SDR and
DDR mode. Data serialization can be up to 6:1 (10:1 if using OSERDES Width Expansion). 3-state serialization
can be up to 4:1. There is a dedicated DDR3 mode to support high-speed memory applications.
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013 www.xilinx.com 283