Xilinx Virtex-6 Manual page 157

IBUFGDS
Primitive: Differential Signaling Dedicated Input Clock Buffer and Optional Delay
Introduction
This design element is a dedicated differential signaling input buffer for connection to the clock buffer (BUFG) or
MMCM. In IBUFGDS, a design-level interface signal is represented as two distinct ports (I and IB), one deemed
the "master" and the other the "slave." The master and the slave are opposite phases of the same logical signal (for
example, MYNET_P and MYNET_N). Optionally, a programmable differential termination feature is available to
help improve signal integrity and reduce external components. Also available is a programmable delay is to
assist in the capturing of incoming data to the device.
Logic Table
Inputs
I
0
0
1
1
Port Descriptions
Port Direction
O Output
IB Input
I Input
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
Put all I/O components on the top-level of the design to help facilitate hierarchical design methods. Connect the I
port directly to the top-level "master" input port of the design, the IB port to the top-level "slave" input port and
the O port to an MMCM, BUFG or logic in which this input is to source. Some synthesis tools infer the BUFG
automatically if necessary, when connecting an IBUFG to the clock resources of the FPGA. Specify the desired
generic/defparam values in order to configure the proper behavior of the buffer.
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
IB
0
1
0
1
Width Function
1 Clock Buffer output
1 Diff_n Clock Buffer Input
1 Diff_p Clock Buffer Input
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Chapter 4: About Design Elements
Outputs
O
No Change
0
1
No Change
Recommended
No
No
No
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