Xilinx Virtex-6 Manual page 280

Chapter 4: About Design Elements
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- OBUFTDS: Differential 3-state Output Buffer
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
OBUFTDS_inst : OBUFTDS
generic map (
IOSTANDARD => "DEFAULT")
port map (
O => O, -- Diff_p output (connect directly to top-level port)
OB => OB, -- Diff_n output (connect directly to top-level port)
I => I, -- Buffer input
T => T -- 3-state enable input
);
-- End of OBUFTDS_inst instantiation
Verilog Instantiation Template
// OBUFTDS: Differential 3-state Output Buffer
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
OBUFTDS #(
.IOSTANDARD("DEFAULT") // Specify the output I/O standard
) OBUFTDS_inst (
.O(O), // Diff_p output (connect directly to top-level port)
.OB(OB), // Diff_n output (connect directly to top-level port)
.I(I), // Buffer input
.T(T) // 3-state enable input
);
// End of OBUFTDS_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
280
Sheets).
Virtex-6 Libraries Guide for HDL Designs
www.xilinx.com UG623 (v 14.5) March 20, 2013