Xilinx Virtex-6 Manual page 176

Chapter 4: About Design Elements
IODELAYE1
Primitive: Input and Output Fixed or Variable Delay Element
Introduction
Every I/O block contains a programmable absolute delay element called IODELAYE1. The IODELAYE1 can be
connected to an input register/ISERDESE1 or output register/OSERDESE1 block or both. IODELAYE1 is a 31-tap,
wraparound, delay element with a calibrated tap resolution. Refer to the Virtex-6 FPGA Data Sheet for delay
values. It can be applied to the combinatorial input path, registered input path, combinatorial output path, or
registered output path. It can also be accessed directly in the FPGA logic. IODELAYE1 allows incoming signals
to be delayed on an individual basis. The tap delay resolution is varied by selecting an IDELAYCTRL reference
clock from the range specified in the Virtex-6 FPGA Data Sheet. The IODELAYE1 resource can function as
an input, output, or bidirectional delay.
Port Descriptions
Port
C
CE
CINVCTRL
CLKIN
CNTVALUEIN[4:0]
CNTVALUEOUT[4:0]
DATAIN
DATAOUT
176
Direction Width Function
Input 1 Clock input used in VARIABLE or VAR_LOADABLE mode.
Input 1 Active high enable increment/decrement function.
Input 1 Dynamically inverts the Clock (C) polarity.
Input 1 Clock Access into the IODELAY (from the IO CLKMUX).
Input 5 Tap counter value from FPGA logic for dynamically loadable
tap value.
5
Output Tap counter value going to FPGA logic for monitoring tap value
Input 1
The DATAIN input is directly driven by the FPGA logic providing
a logic accessible delay line. The data is driven back into the
FPGA logic through the DATAOUT port with a delay set by the
IDELAY_VALUE. DATAIN can be locally inverted. The data
cannot be driven to an IOB.
Output 1 Delayed data from the three data input ports. DATAOUT connects
to the FPGA logic (IDELAY mode), or an IOB (ODELAY mode) or
both (bidirectional delay mode). If used in the bidirectional delay
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Virtex-6 Libraries Guide for HDL Designs
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