Library Unisim; Use Unisim.vcomponents.all - Xilinx Virtex-6 Manual

Chapter 4: About Design Elements
Attribute
INIT_46
INIT_47
INIT_48
INIT_49
INIT_4A
INIT_4B
INIT_4C
INIT_4D
INIT_4E
INIT_4F
INIT_50
INIT_51
INIT_52
INIT_53
INIT_54
INIT_55
INIT_56
INIT_57
SIM_DEVICE
SIM_MONITOR_FILE
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
374
Data
Type Allowed_Values D efault
Hexa- 16'h0000 to
decimal
16'hffff
Hexa-
16'h0000 to
decimal 16'hffff
Hexa- 16'h0000 to
decimal 16'hffff
Hexa- 16'h0000 to
decimal
16'hffff
Hexa-
16'h0000 to
decimal 16'hffff
Hexa- 16'h0000 to
decimal 16'hffff
Hexa- 16'h0000 to
decimal
16'hffff
Hexa-
16'h0000 to
decimal 16'hffff
Hexa- 16'h0000 to
decimal
16'hffff
Hexa-
16'h0000 to
decimal 16'hffff
Hexa- 16'h0000 to
decimal 16'hffff
Hexa- 16'h0000 to
decimal
16'hffff
Hexa-
16'h0000 to
decimal 16'hffff
Hexa- 16'h0000 to
decimal 16'hffff
Hexa- 16'h0000 to
decimal
16'hffff
Hexa-
16'h0000 to
decimal 16'hffff
Hexa- 16'h0000 to
decimal
16'hffff
Hexa-
16'h0000 to
decimal
16'hffff
String "VIRTEX5",
"VIRTEX6"
String String
representing
file name and
location
www.xilinx.com
Description
16'h0000 Test register 3
Test register 4
16'h0000
16'h0000 Sequence register 0
16'h0000 Sequence register 1
16'h0000 Sequence register 2
16'h0000 Sequence register 3
16'h0000 Sequence register 4
Sequence register 5
16'h0000
16'h0000 Sequence register 6
16'h0000 Sequence register 7
16'h0000 Alarm limit register 0
16'h0000 Alarm limit register 1
16'h0000 Alarm limit register 2
16'h0000 Alarm limit register 3
16'h0000 Alarm limit register 4
16'h0000 Alarm limit register 5
16'h0000 Alarm limit register 6
16'h0000 Alarm limit register 7
"VIRTEX5"
Specifies the target device family for
simulation.
design.txt Simulation analog entry file
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013