Xilinx Virtex-6 Manual page 59

Name Direction
WRCOUNT Output
WRERR Output
Input Ports
DI Input
RDCLK Input
RDEN Input
RST Input
WRCLK Input
WREN Input
Configuration Table
This unimacro can be instantiated only. The unimacro is a parameterizable version of the primitive. Please use
the Configuration Table below to correctly configure the unimacro to meet design needs.
DATA_WIDTH
72 - 37
36 - 19
18 - 10
9-5
1-4
Design Entry Method
This unimacro can be instantiated only. It is a parameterizable version of the primitive. Consult the above
Configuration Table to correctly configure this element to meet your design needs.
Instantiation
Inference
CORE Generator™ and wizards
Macro support
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Width
See
Configuration
Table below.
1
See
Configuration
Table below.
1
1
1
1
1
FIFO_SIZE
36kb
36kb
18kb
36kb
18kb
36kb
18kb
36kb
18kb
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Function
FIFO data write pointer.
When the FIFO is full, any additional write operation
generates an error flag.
Data input bus addressed by ADDR.
Clock for Read domain operation.
Read Enable
Asynchronous reset.
Clock for Write domain operation.
Write Enable
WRCOUNT
9
10
9
11
10
12
11
13
12
Yes
No
No
Recommended
Chapter 2: About Unimacros
RDCOUNT
9
10
9
11
10
12
11
13
12
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