Xilinx Virtex-6 Manual page 346

Chapter 4: About Design Elements
ROM128X1
Primitive: 128-Deep by 1-Wide ROM
Introduction
This design element is a 128-word by 1-bit read-only memory. The data output (O) reflects the word selected by
the 7-bit address (A6:A0). The ROM is initialized to a known value during configuration with the INIT=value
parameter. The value consists of 32 hexadecimal digits that are written into the ROM from the most-significant
digit A=FH to the least-significant digit A=0H. An error occurs if the INIT=value is not specified.
Logic Table
Input
I0 I1
0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1
346
I2 I3
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
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Output
O
INIT(0)
INIT(1)
INIT(2)
INIT(3)
INIT(4)
INIT(5)
INIT(6)
INIT(7)
INIT(8)
INIT(9)
INIT(10)
INIT(11)
INIT(12)
INIT(13)
INIT(14)
INIT(15)
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013