Xilinx Virtex-6 Manual page 58

Chapter 2: About Unimacros
FIFO_DUALCLOCK_MACRO
Macro: Dual Clock First-In, First-Out (FIFO) RAM Buffer
Introduction
FPGA devices contain several block RAM memories that can be configured as general-purpose 36kb or 18kb
RAM/ROM memories. Dedicated logic in the block RAM enables you to easily implement FIFOs. The FIFO
can be configured as an 18 kb or 36 kb memory. This unimacro configures the FIFO for using independent read
and writes clocks. Data is read from the FIFO on the rising edge of read clock and written to the FIFO on
the rising edge of write clock.
Depending on the offset between read and write clock edges, the Empty, Almost Empty, Full and Almost Full
flags can deassert one cycle later. Due to the asynchronous nature of the clocks the simulation model only reflects
the deassertion latency cycles listed in the User Guide.
Port Description
Name Direction
Output Ports
ALMOSTEMPTY Output
ALMOSTFULL Output
DO Output
EMPTY Output
FULL Output
RDCOUNT Output
RDERR Output
58
Width Function
1
Almost all valid entries in FIFO have been read.
1
Almost all entries in FIFO memory have been filled.
See
Data output bus addressed by ADDR.
Configuration
Table below.
1 FIFO is empty.
1 All entries in FIFO memory are filled.
See FIFO data read pointer.
Configuration
Table below.
1 When the FIFO is empty, any additional read operation
generates an error flag.
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Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013