Xilinx Virtex-6 Manual page 191

LDCE
Primitive: Transparent Data Latch with Asynchronous Clear and Gate Enable
Introduction
This design element is a transparent data latch with asynchronous clear and gate enable. When the asynchronous
clear input (CLR) is High, it overrides the other inputs and resets the data (Q) output Low. Q reflects the data (D)
input while the gate (G) input and gate enable (GE) are High and CLR is Low. If (GE) is Low, data on (D) cannot
be latched. The data on the (D) input during the High-to-Low gate transition is stored in the latch. The data on
the (Q) output remains unchanged as long as (G) or (GE) remains low.
This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-on
conditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted
by adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic Table
Inputs
CLR GE
1 X
0 0
0 1
0 1
0 1
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
Available Attributes
Attribute Data Type
INIT Binary
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
G
X
X
1
0
↓
Yes
Recommended
No
No
Allowed
Values Default
0, 1 0
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Chapter 4: About Design Elements
Outputs
D Q
X 0
X No Change
D D
X
No Change
D D
Description
Sets the initial value of Q output after configuration.
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