Xilinx Virtex-6 Manual page 28

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Chapter 2: About Unimacros
WRITE_WIDTH_A/B-
DIA/DIB
2
1
18-10
9 - 5
4 - 3
2
1
28
READ_WIDTH_A/B-
DOA/DOB
36-19
18-10
9 - 5
4 - 3
2
1
36-19
18-10
9 - 5
4 - 3
2
1
18-10
9 - 5
4 - 3
2
1
18-10
9 - 5
4 - 3
2
1
18-10
9 - 5
4 - 3
2
1
18-10
9 - 5
4 - 3
2
1
18-10
9 - 5
4 - 3
2
1
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BRAM_SIZE
ADDRA/B
14
36Kb
14
14
14
14
15
36Kb
15
15
15
15
15
15
18Kb
10
11
12
13
14
18Kb
11
11
12
13
14
18Kb
12
12
12
13
14
18Kb
13
13
13
13
14
18Kb
14
14
14
14
14
Virtex-6 Libraries Guide for HDL Designs
WEA/B
1
1
2
1
1
1
1
UG623 (v 14.5) March 20, 2013

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