Xilinx Virtex-6 Manual page 336
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Chapter 4: About Design Elements
Port
RSTRAMARSTRAM
RSTRAMB
RSTREGARSTREG
RSTREGB
SBITERR
WEA[3:0]
WEBWE[7:0]
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
Available Attributes
Attribute
COLLISION CHECK
336
Direction
Width
Input
1
Input
1
Input
1
Input
1
Output
1
Input
4
Input
8
Data Type Allowed Values
String
"ALL",
"GENERATE_X_
ONLY", "NONE",
"WARNING_ONLY"
www.xilinx.com
Function
Synchronous data latch set/reset to value indicated by SRVAL_A.
RSTRAMARSTRAM sets/resets the BRAM data output latch when
DO_REG=0 or 1. If DO_REG=1 there is a cycle of latency between
the internal data latch node that is reset by RSTRAMARSTRAM
and the DO output of the BRAM. This signal is RSTRAMA
on port A when RAM_MODE=TDP and RSTRAM when
RAM_MODE=SDP.
Synchronous data latch set/reset to value indicated by SRVAL_B.
RSTRAMB sets/resets the BRAM data output latch when
DO_REG=0 or 1. If DO_REG=1 there is a cycle of latency between
the internal data latch node that is reset by RSTRAMB and the DO
output of the BRAM. Not used when RAM_MODE=SDP.
Synchronous output register set/reset to value indicated by
SRVAL_A. RSTREGARSTREG sets/resets the output register when
DO_REG=1. RSTREG_PRIORITY_A determines if this signal gets
priority over REGCEAREGCE. This signal is RSTREGA on port A
when RAM_MODE=TDP and RSTREG when RAM_MODE=SDP.
Synchronous output register set/reset to value indicated by
SRVAL_B. RSTREGB sets/resets the output register when
DO_REG=1. RSTREG_PRIORITY_B determines if this signal gets
priority over REGCEB. Not used when RAM_MODE=SDP.
Status output from ECC function to indicate a single bit error was
detected. EN_ECC_READ needs to be TRUE in order to use this
functionality. Not used when RAM_MODE=TDP.
Port A byte-wide write enable. Not used when RAM_MODE=SDP.
See User Guide for WEA mapping for different port widths.
Port B byte-wide write enable/Write enable. See
Resources User Guide
for WEBWE mapping for different port
widths.
Yes
Recommended
Yes
Yes
Default
Description
"ALL"
Allows modification of the simulation
behavior so that if a memory collision
occurs:
•
•
Virtex-6 Libraries Guide for HDL Designs
Virtex®-6 Memory
"ALL" - warning produced and
affected outputs/memory location
go unknown (X)
"WARNING_ONLY" - warning
produced and affected
outputs/memory retain last
value
UG623 (v 14.5) March 20, 2013
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