Xilinx Virtex-7 FPGA VC7203 Getting Started Manual
  1. Manuals
  2. Brands
  3. Xilinx Manuals
  4. Motherboard
  5. Virtex-7 FPGA VC7222 IBERT
  6. Getting started manual

Xilinx Virtex-7 FPGA VC7203 Getting Started Manual

Characterization kit ibert
Hide thumbs Also See for Virtex-7 FPGA VC7203:
Table of Contents

Advertisement

Quick Links

Download this manual
Virtex-7 FPGA VC7203
Characterization Kit IBERT
Getting Started Guide
Vivado Design Suite 2013.2
UG847 (v3.0) July 10, 2013

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the Virtex-7 FPGA VC7203 and is the answer not in the manual?

Questions and answers

Related Manuals for Xilinx Virtex-7 FPGA VC7203

Summary of Contents for Xilinx Virtex-7 FPGA VC7203

  • Page 1 Virtex-7 FPGA VC7203 Characterization Kit IBERT Getting Started Guide Vivado Design Suite 2013.2 UG847 (v3.0) July 10, 2013...

  • Page 2: Revision History

    Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance;...

  • Page 3: Table Of Contents

    Appendix A: Additional Resources Xilinx Resources ............43 Solution Centers .
  • Page 4 VC7203 IBERT Getting Started Guide UG847 (v3.0) July 10, 2013...

  • Page 5: Chapter 1: Vc7203 Ibert Getting Started Guide

    Extracting the Project Files Connecting the GTX Transceivers and Reference Clocks Configuring the FPGA Launching the Vivado Design Suite Software Starting the SuperClock-2 Module Viewing GTX Transceiver Operation Closing the IBERT Demonstration VC7203 IBERT Getting Started Guide www.xilinx.com UG847 (v3.0) July 10, 2013...

  • Page 6: Requirements

    • Xilinx Vivado Design Suite version 2013.2 or higher • PC with a version of the Windows operating system supported by Xilinx Vivado Design Suite Setting Up the VC7203 Board This section describes how to set up the VC7203 board.

  • Page 7: Extracting The Project Files

    The Vivado project files required to run the IBERT demonstrations are located in vc7203_ibert.zip on the SD card provided with the VC7203 board. They are also available online (as collection rdf0272_2013_2.zip) at: www.xilinx.com/vc7203 The ZIP collection also contains two Tcl scripts: add_scm2.tcl and setup_scm2_156_25.tcl, and seven Vivado probe files: vc7203_q113.ltx, vc7203_q114.ltx, vc7203_q115.ltx, vc7203_q116.ltx, vc7203_q117.ltx,...
  • Page 8 All GTX transceiver pins and reference clock pins are routed from the FPGA to a connector pad which interfaces with Samtec BullsEye connectors. Figure 1-2 A shows the connector pad. Figure 1-2 B shows the connector pinout. www.xilinx.com VC7203 IBERT Getting Started Guide UG847 (v3.0) July 10, 2013...

  • Page 9: Attach The Gtx Quad Connector

    Attach the GTX Quad Connector Before connecting the BullsEye cable assembly to the board, firmly secure the blue elastomer seal provided with the cable assembly to the bottom of the connector housing if VC7203 IBERT Getting Started Guide www.xilinx.com UG847 (v3.0) July 10, 2013...

  • Page 10: Gtx Transceiver Clock Connections

    P and N coax cables that are connected to the CLK1 reference clock inputs. Connect these cables to the SuperClock-2 module as follows: CLK1_P coax cable → SMA connector J5 (CLKOUT1_P) on the SuperClock-2 module • www.xilinx.com VC7203 IBERT Getting Started Guide UG847 (v3.0) July 10, 2013...

  • Page 11: Gtx Tx/Rx Loopback Connections

    SMA F-F Adapter RX Coax UG847_c1_07_103112 Figure 1-7: TX-To-RX Loopback Connection Example Figure 1-8 shows the VC7203 board with the cable connections required for the Quad 115 GTX IBERT demonstration. VC7203 IBERT Getting Started Guide www.xilinx.com UG847 (v3.0) July 10, 2013...

  • Page 12: Configuring The Fpga

    The FPGA can also be configured through the Vivado Design Suite software using the .bit files and .ltx probe files which are available online (as collection rdf0272_2013_2.zip) at: www.xilinx.com/vc7203 To configure from the SD card: Insert the SD card provided with the VC7203 board into the SD card reader slot located on the bottom-side (upper-right corner) of the VC7203 board.
  • Page 13 Table 1-1: SD Card Contents and Configuration Addresses Demonstration ADR2 ADR1 ADR0 Design GTX Quad 113 GTX Quad 114 GTX Quad 115 GTX Quad 116 GTX Quad 117 GTX Quad 118 GTX Quad 119 USB/UART VC7203 IBERT Getting Started Guide www.xilinx.com UG847 (v3.0) July 10, 2013...

  • Page 14: Launching The Vivado Design Suite Software

    Start Vivado Design Suite on the host computer and click File > Open Hardware Session (highlighted in Figure 1-10). X-Ref Target - Figure 1-10 Figure 1-10: Vivado Design Suite, Open Hardware Session www.xilinx.com VC7203 IBERT Getting Started Guide UG847 (v3.0) July 10, 2013...
  • Page 15 In the Select Hardware Target window, the Digilent cable appears under Hardware Targets and the JTAG chain contents of the selected cable under Hardware (Figure 1-12). Select digilent_plugin and click Next. Devices VC7203 IBERT Getting Started Guide www.xilinx.com UG847 (v3.0) July 10, 2013...

  • Page 16: Starting The Superclock-2 Module

    SuperClock-2 module. The SuperClock-2 module features two clock-source components: 1) An always-on Si570 crystal oscillator and, 2) an Si5368 jitter-attenuating clock multiplier. Outputs from either device can be used to drive the transceiver reference clocks. www.xilinx.com VC7203 IBERT Getting Started Guide UG847 (v3.0) July 10, 2013...
  • Page 17 Properties window, enter the file path to the Probes file associated with the Q115 IBERT design (vc7203_q115.ltx) (Figure 1-14). X-Ref Target - Figure 1-13 Figure 1-13: Adding the Probes File In the Hardware window, right-click XC7VX485T_1 and select Refresh Device (Figure 1-14). VC7203 IBERT Getting Started Guide www.xilinx.com UG847 (v3.0) July 10, 2013...
  • Page 18 SuperClock-2 module, select Tools > Run Tcl Script (Figure 1-15). In the following Run Script window, navigate to the setup_scm2_156_25.tcl script in the extracted files and click OK. www.xilinx.com VC7203 IBERT Getting Started Guide UG847 (v3.0) July 10, 2013...
  • Page 19 60 to produce an output frequency of 156.250 MHz. Entering a different ROM address changes the reference clock(s) frequency. The complete list of pre-programmed SuperClock-2 frequencies and their associated ROM addresses is provided in Table 1-2, page VC7203 IBERT Getting Started Guide www.xilinx.com UG847 (v3.0) July 10, 2013...
  • Page 20 To view the GTX transceiver operation, click Layout > Serial I/O Analyzer. In the Links window, right-click and select Create Links... or press the Create Links button (Figure 1-19). www.xilinx.com VC7203 IBERT Getting Started Guide UG847 (v3.0) July 10, 2013...
  • Page 21 TX GT and RX GT from the two lists, then press the Add (+) button. For this project, connect the following links: MGT_X1Y8/TX to MGT_X1Y8/RX MGT_X1Y9/TX to MGT_X1Y9/RX MGT_X1Y10/TX to MGT_X1Y10/RX MGT_X1Y11/TX to MGT_X1Y11/RX This is shown in Figure 1-18. VC7203 IBERT Getting Started Guide www.xilinx.com UG847 (v3.0) July 10, 2013...

  • Page 22: Viewing Gtx Transceiver Operation

    The line rate for all four GTX transceivers is 12.5 Gb/s (see Status in Figure 1-19). • The GTX transmitter differential output swing is preset to 250 mV. • Verify that there are no bit errors. www.xilinx.com VC7203 IBERT Getting Started Guide UG847 (v3.0) July 10, 2013...

  • Page 23: Closing The Ibert Demonstration

    81.250 OBSAI 614.400 XAUI 312.500 Aurora 162.500 OC-48 19.440 XAUI 625.000 Aurora 325.000 OC-48 77.760 Generic 66.667 Aurora 650.000 OC-48 155.520 Generic 133.333 CE111 173.370 OC-48 311.040 Generic 166.667 VC7203 IBERT Getting Started Guide www.xilinx.com UG847 (v3.0) July 10, 2013...
  • Page 24 330.000 Generic 395.000 Generic 460.000 Generic 335.000 Generic 400.000 Generic 465.000 Generic 340.000 Generic 405.000 Generic 470.000 Generic 345.000 Generic 410.000 Generic 475.000 Generic 350.000 Generic 415.000 Generic 480.000 www.xilinx.com VC7203 IBERT Getting Started Guide UG847 (v3.0) July 10, 2013...
  • Page 25 330.000 Generic 395.000 Generic 460.000 Generic 335.000 Generic 400.000 Generic 465.000 Generic 340.000 Generic 405.000 Generic 470.000 Generic 345.000 Generic 410.000 Generic 475.000 Generic 350.000 Generic 415.000 Generic 480.000 VC7203 IBERT Getting Started Guide www.xilinx.com UG847 (v3.0) July 10, 2013...

  • Page 26: Creating The Gtx Ibert Core

    GTX Quads with any supported line rate can be created following the same series of steps. For more details on generating IBERT cores, refer to Vivado Design Suite User Guide: Programming and Debugging (UG908). Start the Vivado Design Suite. www.xilinx.com VC7203 IBERT Getting Started Guide UG847 (v3.0) July 10, 2013...
  • Page 27 Figure 1-20). X-Ref Target - Figure 1-20 Figure 1-20: Initial window, Vivado Design Suite When the Create a New Customized IP Location dialog window opens (not shown), click Next. VC7203 IBERT Getting Started Guide www.xilinx.com UG847 (v3.0) July 10, 2013...
  • Page 28 Back on the Manage IP Settings window, select Verilog for Target language, Vivado Simulator for Target simulator, and a directory to save the customized IP (Figure 1-22). Click Finish. www.xilinx.com VC7203 IBERT Getting Started Guide UG847 (v3.0) July 10, 2013...
  • Page 29 Figure 1-22: Manage IP Settings In the Vivado IP Catalog window, open the Debug & Verification folder, then open the Debug folder, and double-click IBERT 7 Series GTX (Figure 1-23). VC7203 IBERT Getting Started Guide www.xilinx.com UG847 (v3.0) July 10, 2013...
  • Page 30 A Customize IP window opens. In the Protocol Definition tab, change LineRate (Gbps) to 12.5, then change Refclk (MHz) to 156.25. Do not change the other defaults (Figure 1-24). www.xilinx.com VC7203 IBERT Getting Started Guide UG847 (v3.0) July 10, 2013...
  • Page 31 In the Protocol Selection tab, select Custom 1 / 12.5 Gbps in the drop-down menu under Protocol Selected next to QUAD_113, and select MGTREFCLK1 113 in the Refclk Selection drop-down menu (Figure 1-25). VC7203 IBERT Getting Started Guide www.xilinx.com UG847 (v3.0) July 10, 2013...
  • Page 32 Package Pin and E18 for N Package Pin (the FPGA pins that the system clock connects to), and make sure the Frequency is set to 200.00 (Figure 1-26). Press OK. A Generate Output Products window opens. Leave the defaults unchanged, and press OK. www.xilinx.com VC7203 IBERT Getting Started Guide UG847 (v3.0) July 10, 2013...
  • Page 33 10. Back to Manage IP, in the Sources window, right-click the IBERT IP and select Open IP Example Design (Figure 1-27). Specify a location to save the design, press OK, and the design opens in a new Vivado design tools window. VC7203 IBERT Getting Started Guide www.xilinx.com UG847 (v3.0) July 10, 2013...
  • Page 34 11. In the new window, select Tools > Run Tcl Script. In the Run Script window, navigate to add_scm2.tcl in the extracted files and press OK. The SuperClock-2 Module Design Sources and Constraints are automatically added to the example design (Figure 1-28). www.xilinx.com VC7203 IBERT Getting Started Guide UG847 (v3.0) July 10, 2013...
  • Page 35 Add the top level ports from top_scm2.v to the module declaration and instantiate the top_scm2 module in the example ibert wrapper (Figure 1-29). Click File > Save File. VC7203 IBERT Getting Started Guide www.xilinx.com UG847 (v3.0) July 10, 2013...
  • Page 36 Figure 1-29: SuperClock-2 in the Example IBERT Wrapper 13. In the Sources window, Design Sources should now reflect that the SuperClock-2 module is part of the example IBERT design. Right-click the IBERT core .xci file in www.xilinx.com VC7203 IBERT Getting Started Guide UG847 (v3.0) July 10, 2013...
  • Page 37 Creating the GTX IBERT Core Design Sources and select Set Out-of-Context (Figure 1-30). Press OK in the Set Partition window that pops up. X-Ref Target - Figure 1-30 Figure 1-30: Set Partition VC7203 IBERT Getting Started Guide www.xilinx.com UG847 (v3.0) July 10, 2013...
  • Page 38 15. When the synthesis is done, click Run Synthesis in the Flow Navigator, which synthesizes the rest of the design. 16. When that synthesis is done, a Synthesis Complete window pops up. Select Open Synthesized Design and click OK (Figure 1-32). www.xilinx.com VC7203 IBERT Getting Started Guide UG847 (v3.0) July 10, 2013...
  • Page 39 17. When the Synthesized Design opens, select dbg_hub in the Netlist window, then select the Debug Core Options tab in the Cell Properties window and change C_USER_SCAN_CHAIN* to 2 (Figure 1-33). Click File > Save Constraints. VC7203 IBERT Getting Started Guide www.xilinx.com UG847 (v3.0) July 10, 2013...
  • Page 40 Figure 1-33: Debug Core Options for dbg_hub 18. In the Flow Navigator under Program and Debug, click Generate Bitstream (Figure 1-34). A window pops up asking if it is ok to launch implementation. Click Yes. www.xilinx.com VC7203 IBERT Getting Started Guide UG847 (v3.0) July 10, 2013...
  • Page 41 Creating the GTX IBERT Core X-Ref Target - Figure 1-34 Figure 1-34: Generate Bitstream 19. When implementation completes, navigate to the project directory and locate the resultant bitstream here: \ibert_7series_gtx_0\example_project\ibert_7series_gtx_0_exampl e\ibert_7series_gtx_0_example.runs\impl_1\. VC7203 IBERT Getting Started Guide www.xilinx.com UG847 (v3.0) July 10, 2013...
  • Page 42 Chapter 1: VC7203 IBERT Getting Started Guide www.xilinx.com VC7203 IBERT Getting Started Guide UG847 (v3.0) July 10, 2013...

  • Page 43: Appendix A: Additional Resources

    The Xilinx Virtex-7 FPGA VC7203 Characterization Kit product page: www.xilinx.com/vc7203 The Virtex-7 FPGA VC7203 Characterization Kit - Known Issues and Release Notes Master Answer Record is 52383. These Xilinx documents provide supplemental material useful with this guide:...
  • Page 44 Appendix A: Additional Resources www.xilinx.com VC7203 IBERT Getting Started Guide UG847 (v3.0) July 10, 2013...
  • Page 45 For any breach by Xilinx of this limited warranty, the exclusive remedy of Customer and the sole liability of Xilinx shall be, at the option of Xilinx, to replace or repair the affected products, or to refund to Customer the price of the affected products. The availability of replacement products is subject to product discontinuation policies at Xilinx.
  • Page 46 Appendix B: Warranty www.xilinx.com VC7203 IBERT Getting Started Guide UG847 (v3.0) July 10, 2013...

Table of Contents