Xilinx Virtex-6 Manual page 360

Chapter 4: About Design Elements
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
Xilinx suggests that you instantiate this in the testbench file and not an implementation file or file used during
synthesis of the design. It may be used in conjunction with the design in order to help determine interaction and
start-up sequences between configuration loading and device start-up. In general, a configuration bitstream file
is to be used in conjunction with this model in order to observe configuration behavior.
More information on simulating and using this component can be found in the Xilinx Synthesis and Simulation
Design Guide. Please refer to that guide for further detail on using this component.
Available Attributes
Attribute Data Type
DEVICE_ID 32-bit
hexadecimal
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- SIM_CONFIG_V6_SERIAL: Behavioral Simulation-only Model of FPGA Serial Configuration
--
-- Xilinx HDL Libraries Guide, version 14.5
SIM_CONFIG_V6_SERIAL_inst : SIM_CONFIG_V6_SERIAL
generic map (
DEVICE_ID => X"00000000")
port map (
DONE => DONE, -- 1-bit bi-directional Done pine
CCLK => CCLK, -- 1-bit input configuration clock
DIN => DIN, -- 1-bit input configuration data
INITB =>INITB, -- 1-bit bi-directional INIT status pin
M => M, -- 3-bit input Mode pins
PROGB => PROGB -- 1-bit input Program pin
);
-- End of SIM_CONFIG_V6_SERIAL_inst instantiation
360
Allowed Values
Valid device ID codes
Virtex-6
-- Specifies the Pre-programmed Device ID value
www.xilinx.com
In testbench or simulation-only file.
No
No
No
Default Description
32'h00000000 Specify the Device ID code for the
target device. Used during bitstream
processing and device identification
reads.
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013