Xilinx Virtex-6 Manual page 299

Available Attributes
Attribute Data Type
INIT
Hexadecimal
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- RAM256X1S: 256-deep by 1-wide positive edge write, asynchronous read
-- single-port distributed LUT RAM
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
RAM256X1S_inst : RAM256X1S
generic map (
INIT => X"0000000000000000000000000000000000000000000000000000000000000000")
port map (
O => O, -- Read/Write port 1-bit output
A => A, -- Read/Write port 8-bit address input
D => D, -- RAM data input
WCLK => WCLK, -- Write clock input
WE => WE -- Write enable input
);
-- End of RAM256X1S_inst instantiation
Verilog Instantiation Template
// RAM256X1S: 256-deep by 1-wide positive edge write, asynchronous read
// single-port distributed LUT RAM
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000)
) RAM256X1S_inst (
.O(O), // Readw/rite port 1-bit output
.A(A), // Readw/rite port 8-bit address input
.WE(WE), // Write enable input
.WCLK(WCLK), // Write clock input
.D(D) // RAM data input
);
// End of RAM256X1S_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Allowed Values Default Description
Any 256-Bit Value All
zeros
Sheets).
www.xilinx.com
Chapter 4: About Design Elements
Specifies the initial contents of the RAM.
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