Xilinx Virtex-6 Manual page 274

Chapter 4: About Design Elements
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- OBUF: Single-ended Output Buffer
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
OBUF_inst : OBUF
generic map (
DRIVE => 12,
IOSTANDARD => "DEFAULT",
SLEW => "SLOW")
port map (
O => O, -- Buffer output (connect directly to top-level port)
I => I -- Buffer input
);
-- End of OBUF_inst instantiation
Verilog Instantiation Template
// OBUF: Single-ended Output Buffer
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
OBUF #(
.DRIVE(12), // Specify the output drive strength
.IOSTANDARD("DEFAULT"), // Specify the output I/O standard
.SLEW("SLOW") // Specify the output slew rate
) OBUF_inst (
.O(O), // Buffer output (connect directly to top-level port)
.I(I) // Buffer input
);
// End of OBUF_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
274
Sheets).
Virtex-6 Libraries Guide for HDL Designs
www.xilinx.com UG623 (v 14.5) March 20, 2013