Xilinx Virtex-6 Manual page 141

Available Attributes
Data
Attribute Type
FARSRC String
FRAME_RBT_IN_ String
FILENAME
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- FRAME_ECC_VIRTEX6: Configuration Frame Error Correction
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
FRAME_ECC_VIRTEX6_inst : FRAME_ECC_VIRTEX6
generic map (
FARSRC => "EFAR",
FRAME_RBT_IN_FILENAME => "NONE"
)
port map (
CRCERROR => CRCERROR,
ECCERROR => ECCERROR,
ECCERRORSINGLE => ECCERRORSINGLE, -- 1-bit output: Output Indicating single-bit Frame ECC error detected.
FAR => FAR,
SYNBIT => SYNBIT,
SYNDROME => SYNDROME,
SYNDROMEVALID => SYNDROMEVALID,
SYNWORD => SYNWORD
);
-- End of FRAME_ECC_VIRTEX6_inst instantiation
Verilog Instantiation Template
// FRAME_ECC_VIRTEX6: Configuration Frame Error Correction
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
FRAME_ECC_VIRTEX6 #(
.FARSRC("EFAR"),
.FRAME_RBT_IN_FILENAME("NONE")
)
FRAME_ECC_VIRTEX6_inst (
.CRCERROR(CRCERROR),
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Allowed_Values Default
"EFAR", "FAR" "EFAR"
String None
representing file
name and location
-- Determines if the output of FAR[23:0] configuration register points
-- to the FAR or EFAR. Sets configuration option register bit CTL0[7].
-- This file is output by the ICAP_VIRTEX6 model and it contains Frame
-- Data information for the Raw Bitstream (RBT) file. The FRAME_ECC
-- model will parse this file, calculate ECC and output any error
-- conditions.
-- 1-bit output: Output indicating a CRC error
-- 1-bit output: Output indicating an ECC error
-- 24-bit output: Frame Address Register Value output
-- 5-bit output: Output bit address of error
-- 13-bit output: Output location of erroneous bit
-- 1-bit output: Frame ECC output indicating the SYNDROME output is
-- valid.
-- 7-bit output: Word output in the frame where an ECC error has been
-- detected
// Determines if the output of FAR[23:0] configuration register points to
// the FAR or EFAR. Sets configuration option register bit CTL0[7].
// This file is output by the ICAP_VIRTEX6 model and it contains Frame
// Data information for the Raw Bitstream (RBT) file. The FRAME_ECC model
// will parse this file, calculate ECC and output any error conditions.
// 1-bit output: Output indicating a CRC error
www.xilinx.com
Chapter 4: About Design Elements
Description
EFAR Determines if the output of FAR[23:0]
configuration register points to the FAR or EFAR.
Sets configuration option register bit CTL0[7].
This file is output by the ICAP_VIRTEX6 model
and it contains Frame Data information for the Raw
Bitstream (RBT) file. The FRAME_ECC model will
parse this file, calculate ECC and output any error
conditions.
141