Xilinx Virtex-6 Manual page 107

VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- CFGLUT5: Reconfigurable 5-input LUT
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
CFGLUT5_inst : CFGLUT5
generic map (
INT => X"00000000")
port map (
CDO => CDO, -- Reconfiguration cascade output
O5 => O5, -- 4-LUT output
O6 => O6, -- 5-LUT output
CDI => CDI, -- Reconfiguration data input
CE => CE, -- Reconfiguration enable input
CLK => CLK, -- Clock input
I0 => I0, -- Logic data input
I1 => I1, -- Logic data input
I2 => I2, -- Logic data input
I3 => I3, -- Logic data input
I4 => I4 -- Logic data input
);
-- End of CFGLUT5_inst instantiation
Verilog Instantiation Template
// CFGLUT5: Reconfigurable 5-input LUT
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
CFGLUT5 #(
.INIT(32'h00000000) // Specify initial LUT contents
) CFGLUT5_inst (
.CDO(CDO), // Reconfiguration cascade output
.O5(O5), // 4-LUT output
.O6(O6), // 5-LUT output
.CDI(CDI), // Reconfiguration data input
.CE(CE), // Reconfiguration enable input
.CLK(CLK), // Clock input
.I0(I0), // Logic data input
.I1(I1), // Logic data input
.I2(I2), // Logic data input
.I3(I3), // Logic data input
.I4(I4) // Logic data input
);
// End of CFGLUT5_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Sheets).
www.xilinx.com
Chapter 4: About Design Elements
107