Xilinx Virtex-6 Manual page 375

-- SYSMON: System Monitor
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
SYSMON_inst : SYSMON
generic map (
-- INIT_40 - INIT_42: System Monitor configuration registers
INIT_40 => X"0000",
INIT_41 => X"0000",
INIT_42 => X"0800",
-- INIT_43 - INIT_47: System Monitor Test registers (do not edit)
INIT_43 => X"0000",
INIT_44 => X"0000",
INIT_45 => X"0000",
INIT_46 => X"0000",
INIT_47 => X"0000",
-- INIT_48 - INIT_4F: Sequence registers for the Channel Sequencer
INIT_48 => X"0000",
INIT_49 => X"0000",
INIT_4A => X"0000",
INIT_4B => X"0000",
INIT_4C => X"0000",
INIT_4D => X"0000",
INIT_4E => X"0000",
INIT_4F => X"0000",
-- INIT_50 - INIT_57: Alarm threshold registers
INIT_50 => X"0000",
INIT_51 => X"0000",
INIT_52 => X"0000",
INIT_53 => X"0000",
INIT_54 => X"0000",
INIT_55 => X"0000",
INIT_56 => X"0000",
INIT_57 => X"0000",
-- Simulation attributes: Set for proper simulation behavior
SIM_DEVICE => "VIRTEX5",
SIM_MONITOR_FILE => "design.txt"
)
port map (
-- Alarm Ports: 3-bit (each) output: ALM, OT
ALM => ALM,
OT => OT,
-- DRP Ports: 16-bit (each) output: Dynamic Reconfiguration Ports
DO => DO,
DRDY => DRDY,
-- Status Ports: 1-bit (each) output: SYSMON status ports
BUSY => BUSY,
CHANNEL => CHANNEL,
EOC => EOC,
EOS => EOS,
JTAGBUSY => JTAGBUSY,
JTAGLOCKED => JTAGLOCKED,
JTAGMODIFIED => JTAGMODIFIED, -- 1-bit output: JTAG Write to the DRP has occurred output
-- Auxiliary Analog-Input Pairs: 16-bit (each) input: VAUXP[15:0], VAUXN[15:0]
VAUXN => VAUXN,
VAUXP => VAUXP,
-- Control and Clock Ports: 1-bit (each) input: Reset and Converstion Start
CONVST => CONVST,
CONVSTCLK => CONVSTCLK,
RESET => RESET,
-- DRP Ports: 7-bit (each) input: Dynamic Reconfiguration Ports
DADDR => DADDR,
DCLK => DCLK,
DEN => DEN,
DI => DI,
DWE => DWE,
-- Dedicated Analog Input Pair: 1-bit (each) input: VP/VN
VN => VN,
VP => VP
);
-- End of SYSMON_inst instantiation
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
-- Must be set to VIRTEX6
-- Analog simulation data file name
-- 3-bit output: output alarm for temp, Vccint and Vccaux
-- 1-bit output: Over-Temperature alarm output
-- 16-bit output: DRP output data bus
-- 1-bit output: DRP data ready output signal
-- 1-bit output: ADC busy output
-- 5-bit output: Channel selection outputs
-- 1-bit output: End of Conversion output
-- 1-bit output: End of Sequence output
-- 1-bit output: JTAG DRP transaction in progress output
-- 1-bit output: JTAG requested DRP port lock output
-- 16-bit input: N-side auxiliary analog input
-- 16-bit input: P-side auxiliary analog input
-- 1-bit input: Convert start input
-- 1-bit input: Convert start input
-- 1-bit input: Active-high reset input
-- 7-bit input: DRP input address bus
-- 1-bit input: DRP clock input
-- 1-bit input: DRP input enable signal
-- 16-bit input: DRP input data bus
-- 1-bit input: DRP write enable input
-- 1-bit input: N-side analog input
-- 1-bit input: P-side analog input
www.xilinx.com
Chapter 4: About Design Elements
375