Xilinx Virtex-6 Manual page 159

IBUFGDS_DIFF_OUT
Primitive: Differential Signaling Input Buffer with Differential Output
Introduction
This design element is an input buffer that supports differential signaling. In IBUFGDS_DIFF_OUT, a design
level interface signal is represented as two distinct ports (I and IB), one deemed the "master" and the other the
"slave." The master and the slave are opposite phases of the same logical signal (for example, MYNET_P and
MYNET_N). The IBUFGDS_DIFF_OUT differs from the IBUFGDS in that it allows internal access to both
phases of the differential signal. Optionally, a programmable differential termination feature is available to help
improve signal integrity and reduce external components.
Logic Table
Inputs
I
0
0
1
1
Port Descriptions
Port Direction
I Input
IB Input
O Output
OB Output
Design Entry Method
Instantiation
Inference
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It is suggested to put all I/O components on the top-level of the design to help facilitate hierarchical design
methods. Connect the I port directly to the top-level "master" input port of the design, the IB port to the top-level
"slave" input port, and the O and OB ports to the logic in which this input is to source. Specify the desired
generic/parameter values in order to configure the proper behavior of the buffer.
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
IB
0
1
0
1
Width Function
1 Diff_p Buffer Input (connect to top-level port in the design).
1 Diff_n Buffer Input (connect to top-level port in the design).
1 Diff_p Buffer Output.
1 Diff_n Buffer Output.
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Chapter 4: About Design Elements
Outputs
O
No Change
0
1
No Change
Recommended
No
No
No
OB
No Change
1
0
No Change
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