Xilinx Virtex-6 Manual page 277

OBUFT
Primitive: 3-State Output Buffer with Active Low Output Enable
Introduction
This design element is a single, 3-state output buffer with input I, output O, and active-Low output enables (T).
This element uses the LVTTL standard and has selectable drive and slew rates using the DRIVE and SLOW or
FAST constraints. The defaults are DRIVE=12 mA and SLOW slew.
When T is Low, data on the inputs of the buffers is transferred to the corresponding outputs. When T is High, the
output is high impedance (off or Z state). OBUFTs are generally used when a single-ended output is needed
with a 3-state capability, such as the case when building bidirectional I/O.
Logic Table
Inputs
T
1
0
0
Port Descriptions
Port Direction
O Output
I Input
T Input
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
I
X
1
0
Width
1
1
1
Yes
Recommended
No
No
www.xilinx.com
Chapter 4: About Design Elements
Outputs
O
Z
1
0
Function
Buffer output (connect directly to top-level port)
Buffer input
3-state enable input
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