Xilinx Virtex-6 Manual page 9

Attribute Data Type
SIM_MODE String
SRVAL Hexadecimal
INIT_00 to Hexadecimal
INIT_7F
INITP_00 to
Hexadecimal
INITP_0F
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- BRAM_SDP_MACRO: Simple Dual Port RAM
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
-- Note - This Unimacro model assumes the port directions to be "downto".
-- Simulation of this model with "to" in the port directions could lead to erroneous results.
-----------------------------------------------------------------------
-- READ_WIDTH | BRAM_SIZE | READ Depth
-- WRITE_WIDTH |
-- ============|===========|=============|==============|============--
-- 37-72 | "36Kb"
-- 19-36 | "36Kb"
-- 19-36 | "18Kb"
-- 10-18 | "36Kb"
-- 10-18 | "18Kb"
-- 5-9 | "36Kb"
-- 5-9 | "18Kb"
-- 3-4 | "36Kb"
-- 3-4 | "18Kb"
-- 2 | "36Kb"
-- 2 | "18Kb"
-- 1 | "36Kb"
-- 1 | "18Kb"
-----------------------------------------------------------------------
BRAM_SDP_MACRO_inst : BRAM_SDP_MACRO
generic map (
BRAM_SIZE => "18Kb", -- Target BRAM, "18Kb" or "36Kb"
DEVICE => "VIRTEX6", -- Target device: "VIRTEX5", "VIRTEX6", "SPARTAN6"
WRITE_WIDTH => 0,
READ_WIDTH => 0,
DO_REG => 0, -- Optional output register (0 or 1)
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL", -- Collision check enable "ALL", "WARNING_ONLY",
SRVAL => X"000000000000000000", --
INIT => X"000000000000000000", --
-- The following INIT_xx declarations specify the initial contents of the RAM
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Allowed Values
"SAFE", "FAST" .
Any 72-Bit Value
Any 256-Bit Value
Any 256-Bit Value
| RDADDR Width |
| WRITE Depth | WRADDR Width |
| 512 | 9-bit
| 1024 | 10-bit
| 512 | 9-bit
| 2048 | 11-bit
| 1024 | 10-bit
| 4096 | 12-bit
| 2048 | 11-bit
| 8192 | 13-bit
| 4096 | 12-bit
| 16384 | 14-bit
| 8192 | 13-bit
| 32768 | 15-bit
| 16384 | 14-bit
-- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
-- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
-- "GENERATE_X_ONLY" or "NONE"
Set/Reset value for port output
Initial values on output port
www.xilinx.com
Chapter 2: About Unimacros
Default Description
"SAFE" This is a simulation only attribute. It
will direct the simulation model to
run in performance-oriented mode
when set to "FAST." Please see the
Synthesis and Simulation Design Guide
for more information.
All zeroes Specifies the output value of on the
DO port upon the assertion of the
synchronous reset (RST) signal.
All zeroes Allows specification of the initial
contents of the 16Kb or 32Kb data
memory array.
All zeroes Allows specification of the initial
contents of the 2Kb or 4Kb parity
data memory array.
--
WE Width --
| 8-bit --
| 4-bit --
| 4-bit --
| 2-bit --
| 2-bit --
| 1-bit --
| 1-bit --
| 1-bit --
| 1-bit --
| 1-bit --
| 1-bit --
| 1-bit --
| 1-bit --
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