Xilinx Virtex-6 Manual page 321

Available Attributes
Attribute Data Type
INIT
Hexadecimal
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- RAM64X1S: 64 x 1 positive edge write, asynchronous read single-port distributed RAM
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
RAM64X1S_inst : RAM64X1S
generic map (
INIT => X"0000000000000000")
port map (
O => O, -- 1-bit data output
A0 => A0, -- Address[0] input bit
A1 => A1, -- Address[1] input bit
A2 => A2, -- Address[2] input bit
A3 => A3, -- Address[3] input bit
A4 => A4, -- Address[4] input bit
A5 => A5, -- Address[5] input bit
D => D, -- 1-bit data input
WCLK => WCLK, -- Write clock input
WE => WE -- Write enable input
);
-- End of RAM64X1S_inst instantiation
Verilog Instantiation Template
// RAM64X1S: 64 x 1 positive edge write, asynchronous read single-port distributed RAM
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
RAM64X1S #(
.INIT(64'h0000000000000000) // Initial contents of RAM
) RAM64X1S_inst (
.O(O), // 1-bit data output
.A0(A0), // Address[0] input bit
.A1(A1), // Address[1] input bit
.A2(A2), // Address[2] input bit
.A3(A3), // Address[3] input bit
.A4(A4), // Address[4] input bit
.A5(A5), // Address[5] input bit
.D(D), // 1-bit data input
.WCLK(WCLK), // Write clock input
.WE(WE) // Write enable input
);
// End of RAM64X1S_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Allowed
Values Default
Any 64-Bit Value All zeros
www.xilinx.com
Chapter 4: About Design Elements
Description
Initializes ROMs, RAMs, registers, and look-up
tables.
Sheets).
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