Xilinx Virtex-6 Manual page 98

Chapter 4: About Design Elements
BUFIODQS
Primitive: Differential Clock Input for Transceiver Reference Clocks
Introduction
This element is the same clock buffer as BUFIO with added dedicated circuitry (ideally used for memory
applications) to optionally remove the extra BUFIO delay and also squelch the I/O Clock after a given burst
length from the strobe. In general, this component should only be used with the Xilinx® Memory Interface
Generator (MIG) product.
Port Descriptions
Port
DQSMASK
I
O
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
Available Attributes
Attribute
DQSMASK_ENABLE
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
98
Direction Width
Input 1
Input 1
Output 1
Data
Type Allowed Values
Boolean FALSE, TRUE
www.xilinx.com
Function
"Squelch" the I/O clock after a given burst length
from strobe.
Clock input port.
Clock output port.
No
No
Recommended
No
Default Description
FALSE Enables the squelch circuitry
Sheets).
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013