Xilinx Virtex-6 Manual page 170

Chapter 4: About Design Elements
IDELAYCTRL
Primitive: IDELAY Tap Delay Value Control
Introduction
This design element must be instantiated when using the IODELAYE1. This occurs when the IDELAY or ISERDES
primitive is instantiated with the IOBDELAY_TYPE attribute set to Fixed or Variable. The IDELAYCTRL module
provides a voltage bias, independent of process, voltage, and temperature variations to the tap-delay line using a
fixed-frequency reference clock, REFCLK. This enables very accurate delay tuning.
Port Descriptions
Port Direction
RDY Output
REFCLK Input
RST Input
RST (Module reset) - Resets the IDELAYCTRL circuitry. The RST signal is an active-high asynchronous reset. To
reset the IDELAYCTRL, assert it High for at least 50 ns.
REFCLK (Reference Clock) - Provides a voltage bias, independent of process, voltage, and temperature
variations, to the tap-delay lines in the IOBs. The frequency of REFCLK must be 200 MHz to guarantee the
tap-delay value specified in the applicable data sheet.
RDY (Ready Output) - Indicates the validity of the reference clock input, REFCLK. When REFCLK disappears
(i.e., REFCLK is held High or Low for one clock period or more), the RDY signal is deasserted.
Design Entry Method
Instantiation
Inference
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Macro support
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Width Function
1 Indicates the validity of the reference clock input, REFCLK. When
REFCLK disappears (i.e., REFCLK is held High or Low for one clock
period or more), the RDY signal is deasserted.
1 Provides a voltage bias, independent of process, voltage, and
temperature variations, to the tap-delay lines in the IOBs. The
frequency of REFCLK must be 200 MHz to guarantee the tap-delay
value specified in the applicable data sheet.
1 Resets the IDELAYCTRL circuitry. The RST signal is an active-high
asynchronous reset. To reset the IDELAYCTRL, assert it High for at
least 50 ns.
Recommended
No
No
No
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Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013