Xilinx Virtex-6 Manual page 247

Available Attributes
Attribute Data Type
INIT
Hexadecimal
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- LUT6_L: 6-input Look-Up Table with local output
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
LUT6_L_inst : LUT6_L
generic map (
INIT => X"0000000000000000") -- Specify LUT Contents
port map (
LO => LO, -- LUT local output
I0 => I0, -- LUT input
I1 => I1, -- LUT input
I2 => I2, -- LUT input
I3 => I3, -- LUT input
I4 => I4, -- LUT input
I5 => I5 -- LUT input
);
-- End of LUT6_L_inst instantiation
Verilog Instantiation Template
// LUT6_L: 6-input Look-Up Table with local output
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
LUT6_L #(
.INIT(64'h0000000000000000)
) LUT6_L_inst (
.LO(LO), // LUT local output
.I0(I0), // LUT input
.I1(I1), // LUT input
.I2(I2), // LUT input
.I3(I3), // LUT input
.I4(I4), // LUT input
.I5(I5) // LUT input
);
// End of LUT6_L_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Allowed Values
Any 64-Bit Value
// Specify LUT Contents
www.xilinx.com
Chapter 4: About Design Elements
Default Description
All zeros Specifies the logic value for the
look-up tables.
Sheets).
247