Xilinx Virtex-6 Manual page 258

Chapter 4: About Design Elements
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
CLKOUT6_DIVIDE => 1,
CLKOUT4_CASCADE => FALSE,
CLOCK_HOLD => FALSE,
DIVCLK_DIVIDE => 1,
REF_JITTER1 => 0.0,
STARTUP_WAIT => FALSE
)
port map (
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
CLKOUT0 => CLKOUT0,
CLKOUT0B => CLKOUT0B,
CLKOUT1 => CLKOUT1,
CLKOUT1B => CLKOUT1B,
CLKOUT2 => CLKOUT2,
CLKOUT2B => CLKOUT2B,
CLKOUT3 => CLKOUT3,
CLKOUT3B => CLKOUT3B,
CLKOUT4 => CLKOUT4,
CLKOUT5 => CLKOUT5,
CLKOUT6 => CLKOUT6,
-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
CLKFBOUT => CLKFBOUT,
CLKFBOUTB => CLKFBOUTB, -- 1-bit output: Inverted CLKFBOUT output
-- Status Port: 1-bit (each) output: MMCM status ports
LOCKED => LOCKED,
-- Clock Input: 1-bit (each) input: Clock input
CLKIN1 => CLKIN1,
-- Control Ports: 1-bit (each) input: MMCM control ports
PWRDWN => PWRDWN,
RST => RST,
-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
CLKFBIN => CLKFBIN
);
-- End of MMCM_BASE_inst instantiation
258
-- Cascase CLKOUT4 counter with CLKOUT6 (TRUE/FALSE)
-- Hold VCO Frequency (TRUE/FALSE)
-- Master division value (1-80)
-- Reference input jitter in UI (0.000-0.999).
-- Not supported. Must be set to FALSE.
-- 1-bit output: CLKOUT0 output
-- 1-bit output: Inverted CLKOUT0 output
-- 1-bit output: CLKOUT1 output
-- 1-bit output: Inverted CLKOUT1 output
-- 1-bit output: CLKOUT2 output
-- 1-bit output: Inverted CLKOUT2 output
-- 1-bit output: CLKOUT3 output
-- 1-bit output: Inverted CLKOUT3 output
-- 1-bit output: CLKOUT4 output
-- 1-bit output: CLKOUT5 output
-- 1-bit output: CLKOUT6 output
-- 1-bit output: Feedback clock output
-- 1-bit output: LOCK output
-- 1-bit input: Power-down input
-- 1-bit input: Reset input
-- 1-bit input: Feedback clock input
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Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013