Xilinx Virtex-6 Manual page 254

Chapter 4: About Design Elements
.CLKOUT4_DIVIDE(1),
.CLKOUT5_DIVIDE(1),
.CLKOUT6_DIVIDE(1),
.CLKOUT4_CASCADE("FALSE"),
.CLOCK_HOLD("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(1),
// REF_JITTER: Reference input jitter in UI (0.000-0.999).
.REF_JITTER1(0.0),
.REF_JITTER2(0.0),
.STARTUP_WAIT("FALSE"),
// USE_FINE_PS: Fine phase shift enable (TRUE/FALSE)
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_USE_FINE_PS("FALSE")
)
MMCM_ADV_inst (
// Clock Outputs: 1-bit (each) output: User configurable clock outputs
.CLKOUT0(CLKOUT0),
.CLKOUT0B(CLKOUT0B),
.CLKOUT1(CLKOUT1),
.CLKOUT1B(CLKOUT1B),
.CLKOUT2(CLKOUT2),
.CLKOUT2B(CLKOUT2B),
.CLKOUT3(CLKOUT3),
.CLKOUT3B(CLKOUT3B),
.CLKOUT4(CLKOUT4),
.CLKOUT5(CLKOUT5),
.CLKOUT6(CLKOUT6),
// DRP Ports: 16-bit (each) output: Dynamic reconfigration ports
.DO(DO),
.DRDY(DRDY),
// Dynamic Phase Shift Ports: 1-bit (each) output: Ports used for dynamic phase shifting of the outputs
.PSDONE(PSDONE),
// Feedback Clocks: 1-bit (each) output: Clock feedback ports
.CLKFBOUT(CLKFBOUT),
.CLKFBOUTB(CLKFBOUTB),
// Status Ports: 1-bit (each) output: MMCM status ports
.CLKFBSTOPPED(CLKFBSTOPPED), // 1-bit output: Feedback clock stopped output
.CLKINSTOPPED(CLKINSTOPPED), // 1-bit output: Input clock stopped output
.LOCKED(LOCKED),
// Clock Inputs: 1-bit (each) input: Clock inputs
.CLKIN1(CLKIN1),
.CLKIN2(CLKIN2),
// Control Ports: 1-bit (each) input: MMCM control ports
.CLKINSEL(CLKINSEL),
.PWRDWN(PWRDWN),
.RST(RST),
// DRP Ports: 7-bit (each) input: Dynamic reconfigration ports
.DADDR(DADDR),
.DCLK(DCLK),
.DEN(DEN),
.DI(DI),
.DWE(DWE),
// Dynamic Phase Shift Ports: 1-bit (each) input: Ports used for dynamic phase shifting of the outputs
.PSCLK(PSCLK),
.PSEN(PSEN),
.PSINCDEC(PSINCDEC),
// Feedback Clocks: 1-bit (each) input: Clock feedback ports
.CLKFBIN(CLKFBIN)
);
// End of MMCM_ADV_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
254
// Cascase CLKOUT4 counter with CLKOUT6 (TRUE/FALSE)
// Hold VCO Frequency (TRUE/FALSE)
// "ZHOLD", "INTERNAL", "EXTERNAL", "CASCADE" or "BUF_IN"
// Master division value (1-80)
// Not supported. Must be set to FALSE.
// 1-bit output: CLKOUT0 output
// 1-bit output: Inverted CLKOUT0 output
// 1-bit output: CLKOUT1 output
// 1-bit output: Inverted CLKOUT1 output
// 1-bit output: CLKOUT2 output
// 1-bit output: Inverted CLKOUT2 output
// 1-bit output: CLKOUT3 output
// 1-bit output: Inverted CLKOUT3 output
// 1-bit output: CLKOUT4 output
// 1-bit output: CLKOUT5 output
// 1-bit output: CLKOUT6 output
// 16-bit output: DRP data output
// 1-bit output: DRP ready output
// 1-bit output: Phase shift done output
// 1-bit output: Feedback clock output
// 1-bit output: Inverted CLKFBOUT
// 1-bit output: LOCK output
// 1-bit input: Primary clock input
// 1-bit input: Secondary clock input
// 1-bit input: Clock select input
// 1-bit input: Power-down input
// 1-bit input: Reset input
// 7-bit input: DRP adrress input
// 1-bit input: DRP clock input
// 1-bit input: DRP enable input
// 16-bit input: DRP data input
// 1-bit input: DRP write enable input
// 1-bit input: Phase shift clock input
// 1-bit input: Phase shift enable input
// 1-bit input: Phase shift increment/decrement input
// 1-bit input: Feedback clock input
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Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013