Xilinx Virtex-6 Manual page 67

Functional Categories
This section categorizes, by function, the circuit design elements described in detail later
in this guide. The elements ( primitives and macros) are listed in alphanumeric order
under each functional category.
Advanced
Arithmetic Functions
Clock Components
Design Element
PCIE_2_0
SYSMON
Design Element
DSP48E1
Design Element
BUFG
BUFGCE
BUFGCE_1
BUFGCTRL
BUFGMUX
BUFGMUX_1
BUFGMUX_CTRL
BUFH
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Config/BSCAN Components
I/O Components
RAM/ROM
Advanced
Description
Primitive: PCI Express version 2.0 compliant port
Primitive: System Monitor
Arithmetic Functions
Description
Primitive: 25x18 Two's Complement Multiplier with
Integrated 48-Bit, 3-Input Adder/Subtracter/Accumulator
or 2-Input Logic Unit
Clock Components
Description
Primitive: Global Clock Buffer
Primitive: Global Clock Buffer with Clock Enable
Primitive: Global Clock Buffer with Clock Enable and
Output State 1
Primitive: Global Clock MUX Buffer
Primitive: Global Clock MUX Buffer
Primitive: Global Clock MUX Buffer with Output State 1
Primitive: 2-to-1 Global Clock MUX Buffer
Primitive: Clock buffer for a single clocking region
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Chapter 3
Registers/Latches
Slice/CLB Primitives
67