Xilinx Virtex-6 Manual page 364

Chapter 4: About Design Elements
Verilog Instantiation Template
// SRL16E: 16-bit shift register LUT with clock enable operating on posedge of clock
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
SRL16E #(
.INIT(16'h0000) // Initial Value of Shift Register
) SRL16E_inst (
.Q(Q), // SRL data output
.A0(A0), // Select[0] input
.A1(A1), // Select[1] input
.A2(A2), // Select[2] input
.A3(A3), // Select[3] input
.CE(CE), // Clock enable input
.CLK(CLK), // Clock input
.D(D) // SRL data input
);
// End of SRL16E_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
364
Sheets).
Virtex-6 Libraries Guide for HDL Designs
www.xilinx.com UG623 (v 14.5) March 20, 2013