Xilinx Virtex-6 Manual page 138

Chapter 4: About Design Elements
)
port map (
-- ECC Signals: 1-bit (each) output: Error Correction Circuitry ports
DBITERR => DBITERR,
ECCPARITY => ECCPARITY,
SBITERR => SBITERR,
-- Read Data: 64-bit (each) output: Read output data
DO => DO,
DOP => DOP,
-- Status: 1-bit (each) output: Flags and other FIFO status outputs
ALMOSTEMPTY => ALMOSTEMPTY,
ALMOSTFULL => ALMOSTFULL,
EMPTY => EMPTY,
FULL => FULL,
RDCOUNT => RDCOUNT,
RDERR => RDERR,
WRCOUNT => WRCOUNT,
WRERR => WRERR,
-- ECC Signals: 1-bit (each) input: Error Correction Circuitry ports
INJECTDBITERR => INJECTDBITERR, -- 1-bit input: Inject a double bit error
INJECTSBITERR => INJECTSBITERR,
-- Read Control Signals: 1-bit (each) input: Read clock, enable and reset input signals
RDCLK => RDCLK,
RDEN => RDEN,
REGCE => REGCE,
RST => RST,
RSTREG => RSTREG,
-- Write Control Signals: 1-bit (each) input: Write clock and enable input signals
WRCLK => WRCLK,
WREN => WREN,
-- Write Data: 64-bit (each) input: Write input data
DI => DI,
DIP => DIP
);
-- End of FIFO36E1_inst instantiation
138
-- 1-bit output: double bit error status output
-- 8-bit output: generated error correction parity
-- 1-bit output: single bit error status output
-- 64-bit output: data output
-- 8-bit output: parity data output
-- 1-bit output: almost empty output flag
-- 1-bit output: almost full output flag
-- 1-bit output: empty output flag
-- 1-bit output: full output flag
-- 13-bit output: read count output
-- 1-bit output: read error output
-- 13-bit output: write count output
-- 1-bit output: write error
-- 1-bit input: read clock input
-- 1-bit input: read enable input
-- 1-bit input: clock enable input
-- 1-bit input: reset input
-- 1-bit input: output register set/reset
-- 1-bit input: write clock input
-- 1-bit input: write enable input
-- 64-bit input: data input
-- 8-bit input: parity input
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Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013