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Virtex-6 Libraries Guide for

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UG623 (v 14.5) March 20, 2013

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Page 1 Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013...
Page 2 Xilinx had been advised of the possibility of the same.
Page 3 Design elements are divided into three main categories: • Macros - These elements are in the UniMacro library in the Xilinx tool, and are used to instantiate primitives that are complex to instantiate by just using the primitives. The synthesis tools will automatically expand the unimacros to their underlying primitives.
Page 4 Chapter 1: Introduction Design Entry Methods For each design element in this guide, Xilinx evaluates four options for using the design element, and recommends what we believe is the best solution for you. The four options are: • Instantiation - This component can be instantiated directly into the design. This method is useful if you want to control the exact placement of the individual blocks.
Page 5 Brief description • Schematic symbol • Logic table (if any) • Port descriptions • Design Entry Method • Available attributes • Example instantiation code • For more information Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 6 Input See Configuration Table Data input bus addressed by WRADDR. Input WRADDR, See Configuration Table Write/Read address input buses. RDADDR Input See Configuration Table Byte-Wide Write enable. Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 7 This unimacro can be instantiated only. It is a parameterizable version of the primitive. Consult the Configuration Table above to correctly configure it to meet your design needs. Instantiation Inference CORE Generator™ and wizards Macro support Recommended Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 8 Care should be taken when changing the value of this attribute. Please see the Synthesis and Simulation Design Guide for more information. Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 9 UNISIM.vcomponents.all; -- BRAM_SDP_MACRO: Simple Dual Port RAM Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 -- Note - This Unimacro model assumes the port directions to be "downto". Simulation of this model with "to" in the port directions could lead to erroneous results.
Page 10 INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000", Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 11 -- The next set of INIT_xx are valid when configured as 36Kb INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 12 -- 1-bit input write port enable -- End of BRAM_SDP_MACRO_inst instantiation Verilog Instantiation Template // BRAM_SDP_MACRO: Simple Dual Port RAM Virtex-6 // Xilinx HDL Libraries Guide, version 14.5 /////////////////////////////////////////////////////////////////////// READ_WIDTH | BRAM_SIZE | READ Depth | RDADDR Width | // WRITE_WIDTH |...
Page 13 // The next set of INIT_xx are valid when configured as 36Kb .INIT_40(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_41(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_42(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_43(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_44(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_45(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_46(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_47(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_48(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_49(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4A(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4B(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4C(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4D(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4E(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4F(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_50(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_51(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_52(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_53(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_54(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_55(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_56(256’h0000000000000000000000000000000000000000000000000000000000000000), Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 14 // Input write enable, width defined by write port depth .WRADDR(WRADDR), // Input write address, width defined by write port depth .WRCLK(WRCLK), // 1-bit input write clock .WREN(WREN) // 1-bit input write port enable Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 15 Chapter 2: About Unimacros // End of BRAM_SDP_MACRO_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 16 See Configuration Table Byte-Wide Write enable. below. Input Write/Read enables. Input Output registers synchronous reset. REGCE Input Output register clock enable input (valid only when DO_REG=1) Input Clock input. Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 17 9 - 5 4 - 3 4 - 3 36-19 36Kb 18-10 9 - 5 4 - 3 36-19 36Kb 18-10 9 - 5 4 - 3 Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 18 4 - 3 18-10 18Kb 9 - 5 4 - 3 18-10 18Kb 9 - 5 4 - 3 18-10 18Kb 9 - 5 4 - 3 Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 19 2Kb or 4Kb parity data memory array. VHDL Instantiation Template Unless they already exist, copy the following two statements and paste them before the entity declaration. Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 20 UNISIM.vcomponents.all; -- BRAM_SINGLE_MACRO: Single Port RAM Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 -- Note - This Unimacro model assumes the port directions to be "downto". Simulation of this model with "to" in the port directions could lead to erroneous results.
Page 21 INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 22 -- Input write enable, width defined by write port depth -- End of BRAM_SINGLE_MACRO_inst instantiation Verilog Instantiation Template // BRAM_SINGLE_MACRO: Single Port RAM Virtex-6 // Xilinx HDL Libraries Guide, version 14.5 ///////////////////////////////////////////////////////////////////// READ_WIDTH | BRAM_SIZE | READ Depth | ADDR Width | // WRITE_WIDTH |...
Page 23 .INIT_16(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256’h0000000000000000000000000000000000000000000000000000000000000000), Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 24 .INIT_5D(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5E(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5F(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_60(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_61(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_62(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_63(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_64(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_65(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_66(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_67(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_68(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_69(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6A(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6B(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6C(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6D(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6E(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6F(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_70(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_71(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_72(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_73(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_74(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_75(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_76(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_77(256’h0000000000000000000000000000000000000000000000000000000000000000), Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 25 // Input write enable, width defined by write port depth // End of BRAM_SINGLE_MACRO_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013...
Page 26 Data output bus addressed by ADDRA. below. Output See Configuration Table Data output bus addressed by ADDRB. below. Input Ports Input See Configuration Table Data input bus addressed by ADDRA. below. Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 27 4 - 3 9 - 5 36-19 36Kb 18-10 9 - 5 4 - 3 4 - 3 36-19 36Kb 18-10 9 - 5 4 - 3 Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 28 4 - 3 18-10 18Kb 9 - 5 4 - 3 18-10 18Kb 9 - 5 4 - 3 18-10 18Kb 9 - 5 4 - 3 Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 29 Care should be taken when changing the value of this attribute. Please see the Synthesis and Simulation Design Guide for more information. Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 30 UNISIM.vcomponents.all; -- BRAM_TDP_MACRO: True Dual Port RAM Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 -- Note - This Unimacro model assumes the port directions to be "downto". Simulation of this model with "to" in the port directions could lead to erroneous results.
Page 31 -- The next set of INIT_xx are valid when configured as 36Kb INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000", Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 32 -- The next set of INIT_xx are valid when configured as 36Kb INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 33 -- End of BRAM_TDP_MACRO_inst instantiation Verilog Instantiation Template // BRAM_TDP_MACRO: True Dual Port RAM Virtex-6 // Xilinx HDL Libraries Guide, version 14.5 ////////////////////////////////////////////////////////////////////////// // DATA_WIDTH_A/B | BRAM_SIZE | RAM Depth | ADDRA/B Width | WEA/B Width // // ===============|===========|===========|===============|=============// 19-36 "36Kb"...
Page 34 .INIT_3F(256’h0000000000000000000000000000000000000000000000000000000000000000), // The next set of INIT_xx are valid when configured as 36Kb .INIT_40(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_41(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_42(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_43(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_44(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_45(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_46(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_47(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_48(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_49(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4A(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4B(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4C(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4D(256’h0000000000000000000000000000000000000000000000000000000000000000), Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 35 // The next set of INITP_xx are valid when configured as 36Kb .INITP_08(256’h0000000000000000000000000000000000000000000000000000000000000000), .INITP_09(256’h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0A(256’h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0B(256’h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0C(256’h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0D(256’h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0E(256’h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0F(256’h0000000000000000000000000000000000000000000000000000000000000000) ) BRAM_TDP_MACRO_inst ( .DOA(DOA), // Output port-A data, width defined by READ_WIDTH_A parameter Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 36 // Input port-B write enable, width defined by Port B depth // End of BRAM_TDP_MACRO_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 37 Variable, see WIDTH_PREADD Preadder data input attribute. MULTIPLIER Input Variable, see Multiplier data input WIDTH_MULTIPLIER attribute. CARRYIN Input Carry input Input Clock Inupt Clock enable LOAD Input Load Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 38 Unless they already exist, copy the following two statements and paste them before the entity declaration. Library UNISIM; use UNISIM.vcomponents.all; -- ADDMACC_MACRO: Add and Multiple Accumulate Function implemented in a DSP48E Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 ADDMACC_MACRO_inst : ADDMACC_MACRO generic map ( DEVICE => "VIRTEX6", -- Target Device: "VIRTEX6", "SPARTAN6"...
Page 39 // Preadder data input, width defined by WIDTH_PREADD parameter .RST(RST) // 1-bit active high synchronous reset // End of ADDMACC_MACRO_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 40 Clock Enable CARRYIN Input Carry In Input Clock Input Synchronous Reset Design Entry Method This unimacro can be instantiated only. It is a parameterizable version of the primitive. Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 41 Library UNISIM; use UNISIM.vcomponents.all; -- ADDSUB_MACRO: Variable width & latency - Adder / Subtractor implemented in a DSP48E Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 ADDSUB_MACRO_inst : ADDSUB_MACRO generic map ( DEVICE => "VIRTEX6", -- Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6"...
Page 42 // 1-bit clock input .RST(RST) // 1-bit active high synchronous reset // End of ADDSUB_MACRO_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 43 High for Up and Low for Down (two-clock latency) Input Synchronous Reset Design Entry Method This unimacro can be instantiated only. It is a parameterizable version of the primitive. Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 44 Unless they already exist, copy the following two statements and paste them before the entity declaration. Library UNISIM; use UNISIM.vcomponents.all; -- COUNTER_LOAD_MACRO: Loadable variable counter implemented in a DSP48E Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 COUNTER_LOAD_MACRO_inst : COUNTER_LOAD_MACRO generic map ( COUNT_BY => X"000000000001", -- Count by value DEVICE => "VIRTEX6", -- Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6"...
Page 45 Chapter 2: About Unimacros // End of COUNTER_LOAD_MACRO_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 46 Synchronous Reset Design Entry Method This unimacro can be instantiated only. It is a parameterizable version of the primitive. Instantiation Inference CORE Generator™ and wizards Macro support Recommended Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 47 Unless they already exist, copy the following two statements and paste them before the entity declaration. Library UNISIM; use UNISIM.vcomponents.all; -- COUNTER_TC_MACRO: Counter with terminal count implemented in a DSP48E Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 COUNTER_TC_MACRO_inst : COUNTER_TC_MACRO generic map ( COUNT_BY => X"000000000001", -- Count by value DEVICE => "VIRTEX6", -- Target Device: "VIRTEX5", "VIRTEX6"...
Page 48 Chapter 2: About Unimacros // End of COUNTER_TC_MACRO_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 49 WIDTH attribute. Input Clock Inupt Clock enable Input Synchronous Reset Design Entry Method This unimacro can be instantiated only. It is a parameterizable version of the primitive. Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 50 Unless they already exist, copy the following two statements and paste them before the entity declaration. Library UNISIM; use UNISIM.vcomponents.all; -- EQ_COMPARE_MACRO: Equality Comparator implemented in a DSP48E Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 EQ_COMPARE_MACRO_inst : EQ_COMPARE_MACRO generic map ( DEVICE => "VIRTEX6", -- Target Device: "VIRTEX5", "VIRTEX6"...
Page 51 .DYNAMIC_PATTERN(DYNAMIC_PATTERN), // Input Dynamic Match/Mask Bus, width determined by WIDTH parameter .RST(RST) // 1-bit input active high reset // End of EQ_COMPARE_MACRO_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 52 Variable width, equals the value In a DSP slice, when LOAD is asserted, loads P of the WIDTH_A attibute plus the with A*B+LOAD_DATA. value of the WIDTH_B attribute. Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 53 Unless they already exist, copy the following two statements and paste them before the entity declaration. Library UNISIM; use UNISIM.vcomponents.all; -- MACC_MACRO: Multiple Accumulate Function implemented in a DSP48E Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 MACC_MACRO_inst : MACC_MACRO generic map ( DEVICE => "VIRTEX6", -- Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6"...
Page 54 .LOAD_DATA(LOAD_DATA), // Load accumulator input data, width determined by WIDTH_P parameter .RST(RST) // 1-bit input active high reset // End of MACC_MACRO_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 55 Synchronous Reset. Design Entry Method This unimacro can be instantiated only. It is a parameterizable version of the primitive. Instantiation Inference CORE Generator™ and wizards Macro support Recommended Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 56 Unless they already exist, copy the following two statements and paste them before the entity declaration. Library UNISIM; use UNISIM.vcomponents.all; -- MULT_MACRO: Multiply Function implemented in a DSP48E Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 MULT_MACRO_inst : MULT_MACRO generic map ( DEVICE => "VIRTEX6", -- Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6"...
Page 57 Chapter 2: About Unimacros .RST(RST) // 1-bit input active high reset // End of MULT_MACRO_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 58 All entries in FIFO memory are filled. RDCOUNT Output FIFO data read pointer. Configuration Table below. RDERR Output When the FIFO is empty, any additional read operation generates an error flag. Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 59 This unimacro can be instantiated only. It is a parameterizable version of the primitive. Consult the above Configuration Table to correctly configure this element to meet your design needs. Instantiation Inference CORE Generator™ and wizards Macro support Recommended Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 60 UNISIM.vcomponents.all; -- FIFO_DUALCLOCK_MACRO: Dual-Clock First-In, First-Out (FIFO) RAM Buffer Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 -- Note - This Unimacro model assumes the port directions to be "downto". Simulation of this model with "to" in the port directions could lead to erroneous results.
Page 61 // 1-bit input write clock .WREN(WREN) // 1-bit input write enable // End of FIFO_DUALCLOCK_MACRO_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 62 WRCOUNT Output See Configuration FIFO data write pointer. Table. WRERR Output When the FIFO is full, any additional write operation generates an error flag. Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 63 This unimacro can be instantiated only. It is a parameterizable version of the primitive. Consult the above Configuration Table to correctly configure this element to meet your design needs. Instantiation Inference CORE Generator™ and wizards Macro support Recommended Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 64 UNISIM.vcomponents.all; -- FIFO_SYNC_MACRO: Synchronous First-In, First-Out (FIFO) RAM Buffer Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 -- Note - This Unimacro model assumes the port directions to be "downto". Simulation of this model with "to" in the port directions could lead to erroneous results.
Page 65 // 1-bit input reset .WREN(WREN) // 1-bit input write enable // End of FIFO_SYNC_MACRO_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 66 Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 67 Primitive: Global Clock MUX Buffer BUFGMUX_1 Primitive: Global Clock MUX Buffer with Output State 1 BUFGMUX_CTRL Primitive: 2-to-1 Global Clock MUX Buffer BUFH Primitive: Clock buffer for a single clocking region Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 68 Primitive: Input Buffer IBUFDS Primitive: Differential Signaling Input Buffer IBUFDS_DIFF_OUT Primitive: Signaling Input Buffer with Differential Output IBUFDS_GTHE1 Primitive: Differential Clock Input for the GTH Transceiver Reference Clocks Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 69 Primitive: 32-Deep by 1-Wide Static Dual Port Synchronous RAM32X1S Primitive: 32-Deep by 1-Wide Static Synchronous RAM RAM32X1S_1 Primitive: 32-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 70 Primitive: Transparent Data Latch with Asynchronous Clear and Gate Enable LDPE Primitive: Transparent Data Latch with Asynchronous Preset and Gate Enable ODDR Primitive: Dedicated Dual Data Rate (DDR) Output Register Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 71 Output SRL16E Primitive: 16-Bit Shift Register Look-Up Table (LUT) with Clock Enable SRLC32E Primitive: 32 Clock Cycle, Variable Length Shift Register Look-Up Table (LUT) with Clock Enable Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 72 Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 73 Schematic symbol (if any) • Logic table (if any) • Port descriptions • Design Entry Method • Available attributes (if any) • Example instantiation code • For more information Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 74 Scan Chain Output. Mirror of TDI input pin to FPGA Input Scan Chain Input. Output Test Mode Select. Fabric connection to TAP. UPDATE Output Scan Register Update instruction. Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 75 Unless they already exist, copy the following two statements and paste them before the entity declaration. Library UNISIM; use UNISIM.vcomponents.all; -- BSCAN_VIRTEX6: Boundary Scan Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 BSCAN_VIRTEX6_inst : BSCAN_VIRTEX6 generic map ( DISABLE_JTAG => FALSE, -- This attribute is unsupported. Please leave it at default. JTAG_CHAIN => 1 -- Value for USER command.
Page 76 // 1-bit input: Data input for USER function // End of BSCAN_VIRTEX6_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 77 Unless they already exist, copy the following two statements and paste them before the entity declaration. Library UNISIM; use UNISIM.vcomponents.all; -- BUFG: Global Clock Buffer Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 BUFG_inst : BUFG port map ( O => O, -- 1-bit output: Clock buffer output I => I...
Page 78 .O(O), // 1-bit output: Clock buffer output .I(I) // 1-bit input: Clock buffer input // End of BUFG_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 79 Unless they already exist, copy the following two statements and paste them before the entity declaration. Library UNISIM; use UNISIM.vcomponents.all; -- BUFGCE: Global Clock Buffer with Clock Enable Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 BUFGCE_inst : BUFGCE port map ( O => O, -- 1-bit output: Clock buffer output CE =>...
Page 80 .CE(CE), // 1-bit input: Clock enable input for I0 input .I(I) // 1-bit input: Primary clock input // End of BUFGCE_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 81 Unless they already exist, copy the following two statements and paste them before the entity declaration. Library UNISIM; use UNISIM.vcomponents.all; -- BUFGCE_1: Global Clock Buffer with Clock Enable and Output State 1 Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 BUFGCE_1_inst : BUFGCE_1 port map ( O => O, -- 1-bit output: Clock buffer output CE =>...
Page 82 .CE(CE), // 1-bit input: Clock enable input for I0 input .I(I) // 1-bit input: Primary clock input // End of BUFGCE_1_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 83 Clock Ignore Input. IGNORE pins are used whenever a designer wants to bypass the switching algorithm executed by the BUFGCTRL. Design Entry Method Instantiation Inference Recommended CORE Generator™ and wizards Macro support Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 84 Unless they already exist, copy the following two statements and paste them before the entity declaration. Library UNISIM; use UNISIM.vcomponents.all; -- BUFGCTRL: Global Clock MUX Buffer Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 BUFGCTRL_inst : BUFGCTRL generic map ( INIT_OUT => 0, -- Initial value of BUFGCTRL output (0/1) PRESELECT_I0 =>...
Page 85 Chapter 4: About Design Elements // End of BUFGCTRL_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 86 Function Input Clock0 input Input Clock1 input Output Clock MUX output Input Clock select input Design Entry Method Instantiation Recommended Inference CORE Generator™ and wizards Macro support Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 87 .I1(I1), // 1-bit input: Clock buffer input (S=1) .S(S) // 1-bit input: Clock buffer select // End of BUFGMUX_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 88 Function Input Clock0 input Input Clock1 input Output Clock MUX output Input Clock select input Design Entry Method Instantiation Inference Recommended CORE Generator™ and wizards Macro support Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 89 .I1(I1), // 1-bit input: Clock buffer input (S=1) .S(S) // 1-bit input: Clock buffer select // End of BUFGMUX_1_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 90 However, it can cause the output clock to appear one clock cycle later. Design Entry Method Instantiation Inference Recommended CORE Generator™ and wizards Macro support Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 91 .I1(I1), // 1-bit input: Clock buffer input (S=1) .S(S) // 1-bit input: Clock buffer select // End of BUFGMUX_CTRL_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 92 The BUFH primitive is provided to allow instantiation capability to access the HCLK clock buffer resources. The use of this component requires manual placement and special consideration and thus is recommended for more advanced users. Please refer to the Virtex-6 FPGA Clocking Resources User Guide (UG362) for details about using this component.
Page 93 .O(O), // 1-bit output: Clock output .I(I) // 1-bit input: Clock input // End of BUFH_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 94 Unless they already exist, copy the following two statements and paste them before the entity declaration. Library UNISIM; use UNISIM.vcomponents.all; -- BUFHCE: HROW Clock Buffer for a Single Clocking Region with Clock Enable Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 BUFHCE_inst : BUFHCE generic map ( INIT_OUT => 0 -- Initial output value port map ( O =>...
Page 95 .CE(CE), // 1-bit input: Active high enable input .I(I) // 1-bit input: Clock input // End of BUFHCE_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 96 Unless they already exist, copy the following two statements and paste them before the entity declaration. Library UNISIM; use UNISIM.vcomponents.all; -- BUFIO: I/O Clock Buffer Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 BUFIO_inst : BUFIO port map ( O => O, -- Buffer output I =>...
Page 97 // Clock buffer output .I(I) // Clock buffer input // End of BUFIO_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 98 This element is the same clock buffer as BUFIO with added dedicated circuitry (ideally used for memory applications) to optionally remove the extra BUFIO delay and also squelch the I/O Clock after a given burst length from the strobe. In general, this component should only be used with the Xilinx® Memory Interface Generator (MIG) product.
Page 99 The Virtex®-6 architecture therefore can have up to four BUFRs per region with two driving from the inner columns out (always present), and two BUFRs per region driving from the outer I/O columns in (when present). In Virtex-6 devices, BUFRs can also directly drive MMCM clock inputs and BUFGs. Port Descriptions...
Page 100 // 1-bit input: Clock buffer input driven by an IBUFG, MMCM or local interconnect // End of BUFR_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com...
Page 101 Connect all inputs and outputs to the design in order to ensure proper operation. Available Attributes Data Allowed Attribute Type Values Default Description ONESHOT Boolean TRUE, FALSE TRUE Specifies the procedure for performing single readback per CAP trigger. Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 102 .CAP(CAP), // 1-bit input: Capture Input .CLK(CLK) // 1-bit input: Clock Input // End of CAPTURE_VIRTEX6_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 103 Carry-MUX data input Input Carry-MUX select line CYINIT Input Carry-in initialization input Input Carry cascade input Design Entry Method Instantiation Inference Recommended CORE Generator™ and wizards Macro support Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 104 // 4-bit carry-MUX data in .S(S) // 4-bit carry-MUX select input // End of CARRY4_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 105 Reconfiguration data cascaded output (optionally connect to the CDI input of a subsequent LUT) Input Reconfiguration data serial input Input Reconfiguration clock Input Active high reconfiguration clock enable Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 106 O5 output. Available Attributes Attribute Data Type Allowed Values Default Description INIT Hexadecimal Any 32-bit Value All zeros Specifies the initial logical expression of this element. Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 107 // Logic data input .I4(I4) // Logic data input // End of CFGLUT5_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 108 Unless they already exist, copy the following two statements and paste them before the entity declaration. Library UNISIM; use UNISIM.vcomponents.all; -- DCIRESET: Digitally Controlled Impedance Reset Component Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 DCIRESET_inst : DCIRESET port map ( LOCKED => LOCKED, -- 1-bit output: LOCK status output RST => RST...
Page 109 Chapter 4: About Design Elements For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 110 Active high shift enable input. Design Entry Method Instantiation Recommended Inference CORE Generator™ and wizards Macro support Connect all inputs and outputs to the design to ensure proper operation. Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 111 // 1-bit input: Active high shift enable input // End of DNA_PORT_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 112 DSP algorithms. Some of the functions capable within the block include multiplication, addition (including pre-adder), subtraction, accumulation, shifting, logical operations, and pattern detection. Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 113 Active High, clock enable for the A port registers. Tie to logic one if not used and AREG=1 or 2. Tie to logic zero if AREG=0. When two registers are used, this is the second sequentially. Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 114 P. PATTERNDETECT Output Active High pattern detection. Detects match of P and the selected PATTERN gated by the MASK. Result arrives on the same cycle as P. Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 115 Selects usage of Pre-adder output (AD) Pipeline Registers. Set to 1 to use the AD Pipeline Registers. ALUMODEREG Integer 1, 0 Set to 1 to register the ALUMODE inputs. Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 116 2) select special masks based on the optionally registered C port. These rounding modes can be used to implement convergent rounding in the DSP slice using the pattern detector as described in the Virtex-6 FPGA DSP48E1 Block User Guide. SEL_PATTERN String "PATTERN", "C"...
Page 117 Unless they already exist, copy the following two statements and paste them before the entity declaration. Library UNISIM; use UNISIM.vcomponents.all; -- DSP48E1: 48-bit Multi-Functional Arithmetic Block Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 DSP48E1_inst : DSP48E1 generic map ( -- Feature Control Attributes: Data Path Selection A_INPUT => "DIRECT", -- Selects A input source, "DIRECT"...
Page 118 -- End of DSP48E1_inst instantiation Verilog Instantiation Template // DSP48E1: 48-bit Multi-Functional Arithmetic Block Virtex-6 // Xilinx HDL Libraries Guide, version 14.5 DSP48E1 #( // Feature Control Attributes: Data Path Selection .A_INPUT("DIRECT"), // Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) .B_INPUT("DIRECT"),...
Page 119 .CED(CED), // 1-bit input: Clock enable input for DREG .CEM(CEM), // 1-bit input: Clock enable input for MREG .CEP(CEP), // 1-bit input: Clock enable input for PREG Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 120 .RSTP(RSTP) // 1-bit input: Reset input for PREG // End of DSP48E1_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 121 Unless they already exist, copy the following two statements and paste them before the entity declaration. Library UNISIM; use UNISIM.vcomponents.all; -- EFUSE_USR: 32-bit non-volatile design ID Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 EFUSE_USR_inst : EFUSE_USR generic map ( SIM_EFUSE_VALUE => X"00000000" -- Value of the 32-bit non-volatile design ID used in simulation port map ( EFUSEUSR =>...
Page 122 // 32-bit output: User E-Fuse register value output // End of EFUSE_USR_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 123 CORE Generator™ and wizards Macro support Available Attributes Data Attribute Type Allowed Values Default Description INIT Binary 0, 1 Sets the initial value of Q output after configuration Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 124 // 1-bit Asynchronous clear input .D(D) // 1-bit Data input // End of FDCE_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 125 CORE Generator™ and wizards Macro support Available Attributes Data Allowed Attribute Type Values Default Description INIT Binary 0, 1 Sets the initial value of Q output after configuration Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 126 // 1-bit Asynchronous preset input .D(D) // 1-bit Data input // End of FDPE_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 127 CORE Generator™ and wizards Macro support Available Attributes Data Attribute Type Allowed Values Default Description INIT Binary 0, 1 Sets the initial value of Q output after configuration Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 128 // 1-bit Synchronous reset input .D(D) // 1-bit Data input // End of FDRE_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 129 CORE Generator™ and wizards Macro support Available Attributes Data Allowed Attribute Type Values Default Description INIT Binary 0, 1 Sets the initial value of Q output after configuration Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 130 // 1-bit Synchronous set input .D(D) // 1-bit Data input // End of FDSE_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 131 DI[31:0] Input FIFO data input bus. DIP[3:0] Input FIFO parity data input bus. DO[31:0] Output FIFO data output bus. Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 132 Specifies whether the FIFO is operating in either dual-clock (two independent clocks) or synchronous (single clock) mode. Dual-clock must use DO_REG=1. FIFO_MODE String "FIFO18", "FIFO18" Selects FIFO18 or FIFO18_36 mode. "FIFO18_36" Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 133 Unless they already exist, copy the following two statements and paste them before the entity declaration. Library UNISIM; use UNISIM.vcomponents.all; -- FIFO18E1: 18KB FIFO (First In, First Out) Block RAM Memory Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 FIFO18E1_inst : FIFO18E1 generic map ( ALMOST_EMPTY_OFFSET => X"0080", -- Sets the almost empty threshold ALMOST_FULL_OFFSET =>...
Page 134 // 32-bit input: data input .DIP(DIP) // 4-bit input: parity input // End of FIFO18E1_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 135 DBITERR Output Status output from ECC function to indicate a double bit error was detected. EN_ECC_READ needs to be TRUE in order to use this functionality. Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 136 FIFO was full. • RDERR indicates that a read occurred while the FIFO was empty. Design Entry Method Instantiation Inference CORE Generator™ and wizards Macro support Recommended Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 137 Unless they already exist, copy the following two statements and paste them before the entity declaration. Library UNISIM; use UNISIM.vcomponents.all; -- FIFO36E1: 36KB FIFO (First In, First Out) Block RAM Memory Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 FIFO36E1_inst : FIFO36E1 generic map ( ALMOST_EMPTY_OFFSET => X"0080", -- Sets the almost empty threshold ALMOST_FULL_OFFSET =>...
Page 138 -- Write Data: 64-bit (each) input: Write input data DI => DI, -- 64-bit input: data input DIP => DIP -- 8-bit input: parity input -- End of FIFO36E1_inst instantiation Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 139 // 64-bit input: data input .DIP(DIP) // 8-bit input: parity input // End of FIFO36E1_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 140 Frame ECC output indicating the SYNDROME output is valid. SYNWORD[6:0] Output Word in the frame where an ECC error has been detected. Design Entry Method Instantiation Recommended Inference CORE Generator™ and wizards Macro support Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 141 Unless they already exist, copy the following two statements and paste them before the entity declaration. Library UNISIM; use UNISIM.vcomponents.all; -- FRAME_ECC_VIRTEX6: Configuration Frame Error Correction Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 FRAME_ECC_VIRTEX6_inst : FRAME_ECC_VIRTEX6 generic map ( FARSRC => "EFAR", -- Determines if the output of FAR[23:0] configuration register points -- to the FAR or EFAR.
Page 142 // 7-bit output: Word output in the frame where an ECC error has been // detected // End of FRAME_ECC_VIRTEX6_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 143 Chapter 4: About Design Elements GTHE1_QUAD Primitive: Gigabit Transceiver Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 144 This design element represents the Virtex®-6 FPGA GTH transceiver. GTH is the highest performance, 10G-optimized configurable transceiver in the Virtex-6 FPGA as part of the HXT family. Refer to Virtex-6 FPGA GTH Transceivers User Guide for detailed information regarding this component. The Virtex-6 FPGA GTH Transceivers Wizard is the preferred tool to generate a wrapper to instantiate a GTHE1_QUAD primitive.
Page 145 The Virtex-6 FPGA RocketIO GTX Transceiver Wizard is the preferred tool to generate a wrapper to instantiate a GTXE1 primitive. The Wizard can be found in the Xilinx® CORE Generator™ tool. Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013...
Page 146 Chapter 4: About Design Elements Design Entry Method To instantiate this component, use the Virtex-6 FPGA RocketIO GTX Transceiver Wizard or an associated core containing the component. Xilinx does not recommend direct instantiation of this component. For More Information •...
Page 147 Xilinx recommends that you put all I/O components on the top-level of the design to help facilitate hierarchical design methods. Connect the I port directly to the top-level input port of the design and the O port to the logic in which this input is to source.
Page 148 // Buffer input (connect directly to top-level port) // End of IBUF_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 149 O port to the logic in which this input is to source. Specify the desired generic/defparam values in order to configure the proper behavior of the buffer. Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013...
Page 150 .IB(IB) // Diff_n buffer input (connect directly to top-level port) // End of IBUFDS_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 151 "slave" input port, and the O and OB ports to the logic in which this input is to source. Specify the desired generic/parameter values in order to configure the proper behavior of the buffer. Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013...
Page 152 // Diff_n buffer input (connect directly to top-level port) // End of IBUFDS_DIFF_OUT_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 153 IBUFGDS_GTHE1 component per GTH quad and it connects directly to the REFCLK pin of the GTHE1_QUAD primitive. Design Entry Method To instantiate this component, use the Virtex-6 FPGA GTH Transceivers Wizard or an associated core containing the component. Xilinx does not recommend direct instantiation of this component. For More Information •...
Page 154 Note The RX and TX MUXes can be chosen independently, but the routes are shared on physical silicon. Design Entry Method To instantiate this component, use the RocketIO™ wizard or an associated core containing the component. Xilinx does not recommend direct instantiation of this component.
Page 155 Library UNISIM; use UNISIM.vcomponents.all; -- IBUFG: Single-ended global clock input buffer Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 IBUFG_inst : IBUFG generic map ( IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards IOSTANDARD =>...
Page 156 // Clock buffer input (connect directly to top-level port) // End of IBUFG_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 157 IBUFG to the clock resources of the FPGA. Specify the desired generic/defparam values in order to configure the proper behavior of the buffer. Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013...
Page 158 .IB(IB) // Diff_n clock buffer input (connect directly to top-level port) // End of IBUFGDS_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 159 "slave" input port, and the O and OB ports to the logic in which this input is to source. Specify the desired generic/parameter values in order to configure the proper behavior of the buffer. Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013...
Page 160 // Diff_n buffer input (connect directly to top-level port) // End of IBUFGDS_DIFF_OUT_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 161 Input Configuration data input bus. O[31:0] Output Configuration data output bus. RDWRB Input Read/Write Select. Design Entry Method Instantiation Recommended Inference CORE Generator™ and wizards Macro support Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 162 Unless they already exist, copy the following two statements and paste them before the entity declaration. Library UNISIM; use UNISIM.vcomponents.all; -- ICAP_VIRTEX6: Internal Configuration Access Port Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 ICAP_VIRTEX6_inst : ICAP_VIRTEX6 generic map ( DEVICE_ID => X"4244093", -- Specifies the pre-programmed Device ID value ICAP_WIDTH =>...
Page 163 // 32-bit input: Configuration data input bus .RDWRB(RDWRB) // 1-bit input: Read/Write Select input // End of ICAP_VIRTEX6_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 164 This design element is a dedicated input register designed to receive external dual data rate (DDR) signals into Xilinx® FPGAs.The IDDR is available with modes that present the data to the FPGA fabric at the time and clock edge they are captured, or on the same clock edge. This feature allows you to avoid additional timing complexities and resource usage.
Page 165 Library UNISIM; use UNISIM.vcomponents.all; -- IDDR: Double Data Rate Input Register with Set, Reset and Clock Enable. Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 IDDR_inst : IDDR generic map ( DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE", "SAME_EDGE" -- or "SAME_EDGE_PIPELINED"...
Page 166 .R(R), // 1-bit reset .S(S) // 1-bit set // End of IDDR_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 167 This design element is a dedicated input register designed to receive external dual data rate (DDR) signals into Xilinx® FPGAs. In general, you should only use the IDDR_2CLK for applications in which two clocks are required to capture the rising and falling data for DDR applications.
Page 168 (R) and set (S) pins to be synchronous to the positive edge of the C clock pin. "ASYNC" specifies an asynchronous set/reset function. Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 169 UNISIM.vcomponents.all; -- IDDR_2CLK: Dual-Clock, Input Double Data Rate Input Register with Set, Reset and Clock Enable. Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 IDDR_2CLK_inst : IDDR_2CLK generic map ( DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE", "SAME_EDGE" -- or "SAME_EDGE_PIPELINED"...
Page 170 (i.e., REFCLK is held High or Low for one clock period or more), the RDY signal is deasserted. Design Entry Method Instantiation Recommended Inference CORE Generator™ and wizards Macro support Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 171 .REFCLK(REFCLK), // 1-bit Reference clock input .RST(RST) // 1-bit Reset input // End of IDELAYCTRL_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 172 Width Function Output Buffer output Inout Buffer inout Input Buffer input Input 3-State enable input Design Entry Method Instantiation Inference Recommended CORE Generator™ and wizards Macro support Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 173 // Buffer input .T(T) // 3-state enable input, high=input, low=output // End of IOBUF_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 174 Buffer output Inout Diff_p inout Inout Diff_n inout Input Buffer input Input 3-state enable input Design Entry Method Instantiation Recommended Inference CORE Generator™ and wizards Macro support Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 175 // Buffer input .T(T) // 3-state enable input, high=input, low=output // End of IOBUFDS_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 176 IODELAYE1 is a 31-tap, wraparound, delay element with a calibrated tap resolution. Refer to the Virtex-6 FPGA Data Sheet for delay values. It can be applied to the combinatorial input path, registered input path, combinatorial output path, or registered output path.
Page 177 O - Connects to an output port or OBUF (output mode). HIGH_PERFOR Boolean TRUE, FALSE TRUE When TRUE, this attribute reduces the MANCE_MODE output jitter. When FALSE, reduces power consumption. The difference in power Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 178 Chapter 4: About Design Elements Data Attribute Type Allowed Values Default Description consumption is quantified in the Xilinx Power Estimator (XPE) tool. IDELAY_TYPE String" "DEFAULT", "FIXED", "DEFAULT" Sets the type of tap delay line. DEFAULT delay "VARIABLE", guarantees zero hold times. FIXED delay VAR_LOADABLE"...
Page 179 // 1-bit input - 3-state input control. Tie high for input-only or internal delay or // tie low for output only. // End of IODELAYE1_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 180 The high-speed secondary clock input (CLKB) is used to clock in the input serial data stream. In any mode other than MEMORY_QDR, connect CLKB to an inverted version of CLK. In Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 181 If ISERDES_MODE="MASTER" and two ISERDES_NODELAY SHIFTOUT2 are to be cascaded, connect to the slave ISERDES_NODELAY IDATASHIFTIN1/2 inputs. Design Entry Method Instantiation Recommended Inference CORE Generator™ and wizards Macro support Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 182 Note OFB_USED should be set to FALSE even if the OFB is used but only for the delaying of the OSERDES output Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 183 Unless they already exist, copy the following two statements and paste them before the entity declaration. Library UNISIM; use UNISIM.vcomponents.all; -- ISERDESE1: Input SERial/DESerializer Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 ISERDESE1_inst : ISERDESE1 generic map ( DATA_RATE => "DDR", -- "SDR" or "DDR"...
Page 184 -- 1-bit input: Active high asynchronous reset input -- SHIFTIN1-SHIFTIN2: 1-bit (each) input: Data width expansion input ports SHIFTIN1 => SHIFTIN1, SHIFTIN2 => SHIFTIN2 -- End of ISERDESE1_inst instantiation Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 185 // SHIFTIN1-SHIFTIN2: 1-bit (each) input: Data width expansion input ports .SHIFTIN1(SHIFTIN1), .SHIFTIN2(SHIFTIN2) // End of ISERDESE1_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 186 Macro support Xilinx suggests that you instantiate this in a testbench file and not an implementation file or file used during synthesis of the design. It may be used in conjunction with the design in order to help determine interaction and start-up sequences between configuration loading and device start-up.
Page 187 Unless they already exist, copy the following two statements and paste them before the entity declaration. Library UNISIM; use UNISIM.vcomponents.all; -- JTAG_SIM_VIRTEX6: JTAG Interface Simulation Model Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 JTAG_SIM_VIRTEX6_inst : JTAG_SIM_VIRTEX6 generic map ( PART_NAME => "LX75T") -- Specify target V6 device. Possible values are: -- "CX130T","CX195T","CX240T","CX75T","HX250T", -- "HX255T","HX380T","HX45T","HX565T",...
Page 188 Chapter 4: About Design Elements For More Information • See the Synthesis and Simulation Design Guide (UG626). • See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 189 Unless they already exist, copy the following two statements and paste them before the entity declaration. Library UNISIM; use UNISIM.vcomponents.all; -- KEEPER: I/O Buffer Weak Keeper Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 KEEPER_inst : KEEPER port map ( O => O -- Keeper output (connect directly to top-level port)
Page 190 // Keeper output (connect directly to top-level port) // End of KEEPER_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 191 CORE Generator™ and wizards Macro support Available Attributes Allowed Attribute Data Type Values Default Description INIT Binary 0, 1 Sets the initial value of Q output after configuration. Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 192 // Gate input .GE(GE) // Gate enable input // End of LDCE_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 193 Available Attributes Attribute Data Type Allowed Values Default Description INIT Binary 0, 1 Specifies the initial value upon power-up or the assertion of GSR for the (Q) port. Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 194 // Gate input .GE(GE) // Gate enable input // End of LDPE_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 195 Logic Table Inputs Outputs INIT[0] INIT[1] INIT = Binary number assigned to the INIT attribute Design Entry Method Instantiation Inference Recommended CORE Generator™ and wizards Macro support Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 196 // LUT general output .I0(I0) // LUT input // End of LUT1_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 197 Inference Recommended CORE Generator™ and wizards Macro support Available Attributes Attribute Data Type Allowed Values Default Description INIT Hexadecimal Any 2-Bit Value All zeros Initializes look-up tables. Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 198 // LUT general output .I0(I0) // LUT input // End of LUT1_D_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 199 Inference Recommended CORE Generator™ and wizards Macro support Available Attributes Attribute Data Type Allowed Values Default Description INIT Hexadecimal Any 2-Bit Value All zeros Initializes look-up tables. Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 200 .LO(LO), // LUT local output .I0(I0) // LUT input // End of LUT1_L_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 201 INIT[2] INIT[3] INIT = Binary equivalent of the hexadecimal number assigned to the INIT attribute Design Entry Method Instantiation Inference Recommended CORE Generator™ and wizards Macro support Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 202 .I0(I0), // LUT input .I1(I1) // LUT input // End of LUT2_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 203 Inference Recommended CORE Generator™ and wizards Macro support Available Attributes Attribute Data Type Allowed Values Default Description INIT Hexadecimal Any 4-Bit Value All zeros Initializes look-up tables. Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 204 .I0(I0), // LUT input .I1(I1) // LUT input // End of LUT2_L_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 205 INIT[2] INIT[3] INIT = Binary equivalent of the hexadecimal number assigned to the INIT attribute Design Entry Method Instantiation Inference Recommended CORE Generator™ and wizards Macro support Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 206 .I0(I0), // LUT input .I1(I1) // LUT input // End of LUT2_L_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 207 However, this method does require the code to first specify the appropriate parameters. Logic Table Inputs Outputs INIT[0] INIT[1] INIT[2] INIT[3] INIT[4] INIT[5] INIT[6] INIT[7] INIT = Binary equivalent of the hexadecimal number assigned to the INIT attribute Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 208 .I1(I1), // LUT input .I2(I2) // LUT input // End of LUT3_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 209 INIT[7] INIT[7] INIT = Binary equivalent of the hexadecimal number assigned to the INIT attribute Design Entry Method Instantiation Inference Recommended CORE Generator™ and wizards Macro support Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 210 .I1(I1), // LUT input .I2(I2) // LUT input // End of LUT3_D_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 211 However, this method does require the code to first specify the appropriate parameters. Logic Table Inputs Outputs INIT[0] INIT[1] INIT[2] INIT[3] INIT[4] INIT[5] INIT[6] INIT[7] INIT = Binary equivalent of the hexadecimal number assigned to the INIT attribute Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 212 .I1(I1), // LUT input .I2(I2) // LUT input // End of LUT3_L_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 213 However, this method does require the code to first specify the appropriate parameters. Logic Table Inputs Outputs INIT[0] INIT[1] INIT[2] INIT[3] INIT[4] INIT[5] INIT[6] INIT[7] INIT[8] INIT[9] INIT[10] INIT[11] Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 214 Unless they already exist, copy the following two statements and paste them before the entity declaration. Library UNISIM; use UNISIM.vcomponents.all; -- LUT4: 4-input Look-Up Table with general output Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 LUT4_inst : LUT4 generic map ( INIT => X"0000") port map ( O =>...
Page 215 .I2(I2), // LUT input .I3(I3) // LUT input // End of LUT4_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 216 INIT[0] INIT[1] INIT[1] INIT[2] INIT[2] INIT[3] INIT[3] INIT[4] INIT[4] INIT[5] INIT[5] INIT[6] INIT[6] INIT[7] INIT[7] INIT[8] INIT[8] INIT[9] INIT[9] INIT[10] INIT[10] INIT[11] INIT[11] INIT[12] INIT[12] INIT[13] INIT[13] Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 217: Table Of Contents
Unless they already exist, copy the following two statements and paste them before the entity declaration. Library UNISIM; use UNISIM.vcomponents.all; -- LUT4_D: 4-input Look-Up Table with general and local outputs Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 LUT4_D_inst : LUT4_D generic map ( INIT => X"0000") port map ( LO =>...
Page 218 .I2(I2), // LUT input .I3(I3) // LUT input // End of LUT4_D_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 219: Inputs I3
However, this method does require the code to first specify the appropriate parameters. Logic Table Inputs Outputs INIT[0] INIT[1] INIT[2] INIT[3] INIT[4] INIT[5] INIT[6] INIT[7] INIT[8] INIT[9] INIT[10] INIT[11] INIT[12] Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 220: Instantiation Inference
Unless they already exist, copy the following two statements and paste them before the entity declaration. Library UNISIM; use UNISIM.vcomponents.all; -- LUT4_L: 4-input Look-Up Table with local output Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 LUT4_L_inst : LUT4_L generic map ( INIT => X"0000") port map ( LO =>...
Page 221: I0(I0), // Lut Input
.I2(I2), // LUT input .I3(I3) // LUT input // End of LUT4_L_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 222 However, this method does require the code to first specify the appropriate parameters. Logic Table Inputs Outputs INIT[0] INIT[1] INIT[2] INIT[3] INIT[4] INIT[5] Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 223 INIT = Binary equivalent of the hexadecimal number assigned to the INIT attribute Port Description Name Direction Width Function 5-LUT output Output I0, I1, I2, I3, I4 Input LUT inputs Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 224 .I3(I3), // LUT input .I4(I4) // LUT input // End of LUT5_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 225 However, this method does require the code to first specify the appropriate parameters. Logic Table Inputs Outputs INIT[0] INIT[0] INIT[1] INIT[1] INIT[2] INIT[2] INIT[3] INIT[3] INIT[4] INIT[4] INIT[5] INIT[5] Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 226: Outputs Olo
INIT = Binary equivalent of the hexadecimal number assigned to the INIT attribute Port Description Name Direction Width Function 5-LUT output Output Output 5-LUT output for internal CLB connection I0, I1, I2, I3, I4 Input LUT inputs Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 227: Design Entry Method
Unless they already exist, copy the following two statements and paste them before the entity declaration. Library UNISIM; use UNISIM.vcomponents.all; -- LUT5_D: 5-input Look-Up Table with general and local outputs Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 LUT5_D_inst : LUT5_D generic map ( INIT => X"00000000") -- Specify LUT contents port map ( LO =>...
Page 228 Chapter 4: About Design Elements For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 229 However, this method does require the code to first specify the appropriate parameters. Logic Table Inputs Outputs INIT[0] INIT[1] INIT[2] INIT[3] INIT[4] INIT[5] Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 230 INIT = Binary equivalent of the hexadecimal number assigned to the INIT attribute Port Description Name Direction Width Function Output 6/5-LUT output for internal CLB connection I0, I1, I2, I3, I4 Input LUT inputs Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 231: I0(I0), // Lut Input
.I3(I3), // LUT input .I4(I4) // LUT input // End of LUT5_L_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 232 However, this method does require the code to first specify the appropriate parameters. Logic Table Inputs Outputs INIT[0] INIT[1] INIT[2] Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 233 INIT[13] INIT[14] INIT[15] INIT[16] INIT[17] INIT[18] INIT[19] INIT[20] INIT[21] INIT[22] INIT[23] INIT[24] INIT[25] INIT[26] INIT[27] INIT[28] INIT[29] INIT[30] INIT[31] INIT[32] INIT[33] INIT[34] INIT[35] INIT[36] INIT[37] INIT[38] INIT[39] Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 234 Direction Width Function Output 6/5-LUT output I0, I1, I2, I3, I4, I5 Input LUT inputs Design Entry Method Instantiation Inference Recommended CORE Generator™ and wizards Macro support Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 235: Xilinx Hdl Libraries Guide, Version
.I4(I4), // LUT input .I5(I5) // LUT input // End of LUT6_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 236 However, this method does require the code to first specify the appropriate parameters. Logic Table Inputs Outputs INIT[0] INIT[0] INIT[1] INIT[1] INIT[2] INIT[2] INIT[3] INIT[3] INIT[4] INIT[4] Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 237 INIT[30] INIT[31] INIT[31] INIT[0] INIT[32] INIT[1] INIT[33] INIT[2] INIT[34] INIT[3] INIT[35] INIT[4] INIT[36] INIT[5] INIT[37] INIT[6] INIT[38] INIT[7] INIT[39] INIT[8] INIT[40] INIT[9] INIT[41] INIT[10] INIT[42] INIT[11] INIT[43] Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 238 CORE Generator™ and wizards Macro support Available Attributes Attribute Data Type Allowed Values Default Description INIT Hexadecimal Any 64-Bit Value All zeros Specifies the LUT5/6 output function. Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 239: Verilog Instantiation Template
// 1-bit LUT input (fast MUX select only available to O6 output) // End of LUT6_2_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013...
Page 240 However, this method does require the code to first specify the appropriate parameters. Logic Table Inputs Outputs INIT[0] INIT[0] INIT[1] INIT[1] INIT[2] INIT[2] Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 241 INIT[26] INIT[27] INIT[27] INIT[28] INIT[28] INIT[29] INIT[29] INIT[30] INIT[30] INIT[31] INIT[31] INIT[32] INIT[32] INIT[33] INIT[33] INIT[34] INIT[34] INIT[35] INIT[35] INIT[36] INIT[36] INIT[37] INIT[37] INIT[38] INIT[38] INIT[39] INIT[39] Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 242 Output 6/5-LUT output Output 5-LUT output I0, I1, I2, I3, I4, I5 Input LUT inputs Design Entry Method Instantiation Inference Recommended CORE Generator™ and wizards Macro support Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 243 .I4(I4), // LUT input .I5(I5) // LUT input // End of LUT6_D_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 244 However, this method does require the code to first specify the appropriate parameters. Logic Table Inputs Outputs INIT[0] INIT[1] Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 245 INIT[12] INIT[13] INIT[14] INIT[15] INIT[16] INIT[17] INIT[18] INIT[19] INIT[20] INIT[21] INIT[22] INIT[23] INIT[24] INIT[25] INIT[26] INIT[27] INIT[28] INIT[29] INIT[30] INIT[31] INIT[32] INIT[33] INIT[34] INIT[35] INIT[36] INIT[37] INIT[38] Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 246 6/5-LUT output or internal CLB connection I0, I1, I2, I3, I4, I5 Input LUT inputs Design Entry Method Instantiation Inference Recommended CORE Generator™ and wizards Macro support Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 247 .I4(I4), // LUT input .I5(I5) // LUT input // End of LUT6_L_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 248 Function CLKFBIN Input Feedback clock input. CLKFBOUT Output Dedicated MMCM feedback output. CLKFBOUTB Output Inverted CLKFBOUT. CLKFBSTOPPED Output Status pin indicating that the feedback clock has stopped. Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 249 Asynchronous reset signal.The MMCM will synchronously re-enable itself when this signal is released (i.e., MMCM re-enabled). A reset is not required when the input clock conditions change (e.g., frequency). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 250 CLKOUT4_CASCADE Boolean FALSE, TRUE FALSE Cascades the output divider (counter) into the input of the CLKOUT4 divider for an output clock divider that is greater than 128. Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 251 This attribute is not supported. CLKFBOUT_USE_ Boolean FALSE, TRUE FALSE CLKFBOUT Counter variable fine phase FINE_PS shift enable CLKOUT[0:6]_USE_ Boolean FALSE, TRUE FALSE CLKOUT[1:6] variable fine phase shift FINE_PS enable. Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 252 Unless they already exist, copy the following two statements and paste them before the entity declaration. Library UNISIM; use UNISIM.vcomponents.all; -- MMCM_ADV: Advanced Mixed Mode Clock Manager Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 MMCM_ADV_inst : MMCM_ADV generic map ( BANDWIDTH => "OPTIMIZED", -- Jitter programming ("HIGH","LOW","OPTIMIZED") CLKFBOUT_MULT_F =>...
Page 253 -- 1-bit input: Feedback clock input -- End of MMCM_ADV_inst instantiation Verilog Instantiation Template // MMCM_ADV: Advanced Mixed Mode Clock Manager Virtex-6 // Xilinx HDL Libraries Guide, version 14.5 MMCM_ADV #( .BANDWIDTH("OPTIMIZED"), // Jitter programming ("HIGH","LOW","OPTIMIZED") .CLKFBOUT_MULT_F(5.0), // Multiply value for all CLKOUT (5.0-64.0).
Page 254 // Feedback Clocks: 1-bit (each) input: Clock feedback ports .CLKFBIN(CLKFBIN) // 1-bit input: Feedback clock input // End of MMCM_ADV_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 255 (bypassed) to 128. The output clocks are phase aligned to each other (unless phase shifted) and aligned to the input clock with a proper feedback configuration. CLKOUT[0:3]B Output 4, 1-bit Inverted CLKOUT[0:3]. Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 256 0.001 to 0.500 Specifies the Duty Cycle of the associated 0.999 CYCLE digit Float CLKOUT clock output in percentage (for instance, 0.50 will generate a 50% duty cycle). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 257 Unless they already exist, copy the following two statements and paste them before the entity declaration. Library UNISIM; use UNISIM.vcomponents.all; -- MMCM_BASE: Base Mixed Mode Clock Manager Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 MMCM_BASE_inst : MMCM_BASE generic map ( BANDWIDTH => "OPTIMIZED", -- Jitter programming ("HIGH","LOW","OPTIMIZED") CLKFBOUT_MULT_F =>...
Page 258 -- 1-bit input: Reset input -- Feedback Clocks: 1-bit (each) input: Clock feedback ports CLKFBIN => CLKFBIN -- 1-bit input: Feedback clock input -- End of MMCM_BASE_inst instantiation Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 259 Chapter 4: About Design Elements Verilog Instantiation Template // MMCM_BASE: Base Mixed Mode Clock Manager Virtex-6 // Xilinx HDL Libraries Guide, version 14.5 MMCM_BASE #( .BANDWIDTH("OPTIMIZED"), // Jitter programming ("HIGH","LOW","OPTIMIZED") .CLKFBOUT_MULT_F(5.0), // Multiply value for all CLKOUT (5.0-64.0). .CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB (0.00-360.00).
Page 260 Chapter 4: About Design Elements For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 261 Input (tie to MUXF6 LO out) Input Input (tie to MUXF6 LO out) Input Input select to MUX Design Entry Method Instantiation Inference Recommended CORE Generator™ and wizards Macro support Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 262 // Input (tie to LUT6 O6 pin) .S(S) // Input select to MUX // End of MUXF7_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 263 Input (tie to MUXF6 LO out) Input Input (tie to MUXF6 LO out) Input Input select to MUX Design Entry Method Instantiation Inference Recommended CORE Generator™ and wizards Macro support Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 264 // Input (tie to LUT6 O6 pin) .S(S) // Input select to MUX // End of MUXF7_D_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 265 Output of MUX to local routing Input Input Input Input Input Input select to MUX Design Entry Method Instantiation Inference Recommended CORE Generator™ and wizards Macro support Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 266 // Input (tie to LUT6 O6 pin) .S(S) // Input select to MUX // End of MUXF7_L_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 267 Input (tie to MUXF7 LO out) Input Input (tie to MUXF7 LO out) Input Input select to MUX Design Entry Method Instantiation Inference Recommended CORE Generator™ and wizards Macro support Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 268 // Input (tie to MUXF7 LO out) .S(S) // Input select to MUX // End of MUXF8_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 269 Input (tie to MUXF7 LO out) Input Input (tie to MUXF7 LO out) Input Input select to MUX Design Entry Method Instantiation Inference Recommended CORE Generator™ and wizards Macro support Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 270 // Input (tie to MUXF7 LO out) .S(S) // Input select to MUX // End of MUXF8_D_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 271 Input (tie to MUXF7 LO out) Input Input (tie to MUXF7 LO out) Input Input select to MUX Design Entry Method Instantiation Inference Recommended CORE Generator™ and wizards Macro support Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 272 // Input (tie to MUXF7 LO out) .S(S) // Input select to MUX // End of MUXF8_L_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 273 String "SLOW" or "FAST" "SLOW" Specifies the slew rate of the output driver. Consult the product Data Sheet for recommendations of the best setting for this attribute. Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 274 // Buffer output (connect directly to top-level port) .I(I) // Buffer input // End of OBUF_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 275 CORE Generator™ and wizards Macro support Available Attributes Data Allowed Attribute Type Values Default Description IOSTANDARD String "DEFAULT" See Data Sheet Assigns an I/O standard to the element. Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 276 // Diff_n output (connect directly to top-level port) .I(I) // Buffer input // End of OBUFDS_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 277 Output Buffer output (connect directly to top-level port) Input Buffer input Input 3-state enable input Design Entry Method Instantiation Inference Recommended CORE Generator™ and wizards Macro support Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 278 // Buffer input .T(T) // 3-state enable input // End of OBUFT_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 279 CORE Generator™ and wizards Macro support Available Attributes Data Attribute Type Allowed Values Default Description IOSTANDARD String See Data Sheet "DEFAULT" Assigns an I/O standard to the element. Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 280 // Buffer input .T(T) // 3-state enable input // End of OBUFTDS_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 281 Set - Active High asynchronous set pin. This pin can also be Synchronous depending on the SRTYPE attribute. Design Entry Method Instantiation Recommended Inference CORE Generator™ and wizards Macro support Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 282 .R(R), // 1-bit reset .S(S) // 1-bit set // End of ODDR_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 283 DDR mode. Data serialization can be up to 6:1 (10:1 if using OSERDES Width Expansion). 3-state serialization can be up to 4:1. There is a dedicated DDR3 mode to support high-speed memory applications. Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013...
Page 284 D1 will appear first at OQ. This port connects the output of the data parallel-to-serial converter to the data input of the IOB. This port can not drive the IODELAYE1; the OFB pin must be used. Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 285 MEMORY_DDR3 mode for DDR3 applications. When not using MEMORY_DDR3 mode, connect this port to GND. Design Entry Method Instantiation Recommended Inference CORE Generator™ and wizards Macro support Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 286 Unless they already exist, copy the following two statements and paste them before the entity declaration. Library UNISIM; use UNISIM.vcomponents.all; -- OSERDESE1: Output SERial/DESerializer Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 OSERDESE1_inst : OSERDESE1 generic map ( DATA_RATE_OQ => "DDR", -- "SDR" or "DDR"...
Page 287 -- T1 - T4: 1-bit (each) input: Parallel 3-state inputs T1 => T1, T2 => T2, T3 => T3, T4 => T4 -- End of OSERDESE1_inst instantiation Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 288 // T1 - T4: 1-bit (each) input: Parallel 3-state inputs .T1(T1), .T2(T2), .T3(T3), .T4(T4) // End of OSERDESE1_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 289 Chapter 4: About Design Elements PCIE_2_0 Primitive: PCI Express version 2.0 compliant port Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 290 PCIE_2_0 software primitive, connects the interfaces to the correct FPGA resources, sets all attributes, and presents a simple, user-friendly interface. Design Entry Method To instantiate this component, use the PCI EXPRESS core or an associated core containing the component. Xilinx does not recommend direct instantiation of this component. For More Information •...
Page 291 Unless they already exist, copy the following two statements and paste them before the entity declaration. Library UNISIM; use UNISIM.vcomponents.all; -- PULLDOWN: I/O Buffer Weak Pull-down Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 PULLDOWN_inst : PULLDOWN port map ( O => O -- Pulldown output (connect directly to top-level port)
Page 292 // Pulldown output (connect directly to top-level port) // End of PULLDOWN_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 293 Unless they already exist, copy the following two statements and paste them before the entity declaration. Library UNISIM; use UNISIM.vcomponents.all; -- PULLUP: I/O Buffer Weak Pull-up Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 PULLUP_inst : PULLUP port map ( O => O -- Pullup output (connect directly to top-level port)
Page 294 // Pullup output (connect directly to top-level port) // End of PULLUP_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 295 An optional INIT attribute consisting of a 128-bit Hexadecimal value can be specified to indicate the initial contents of the RAM. If left unspecified, the initial contents default to all zeros. Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 296 Library UNISIM; use UNISIM.vcomponents.all; -- RAM128X1D: 128-deep by 1-wide positive edge write, asynchronous read dual-port distributed LUT RAM Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 RAM128X1D_inst : RAM128X1D generic map ( INIT => X"00000000000000000000000000000000") port map ( DPO => DPO, -- Read/Write port 1-bit output SPO =>...
Page 297 Chapter 4: About Design Elements For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 298 An optional INIT attribute consisting of a 256-bit Hexadecimal value can be specified to indicate the initial contents of the RAM. If left unspecified, the initial contents default to all zeros. Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 299 .WCLK(WCLK), // Write clock input .D(D) // RAM data input // End of RAM256X1S_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 300 ADDRB) Input Write data inputs addressed by ADDRD (read output is addressed by ADDRC) Input Write data inputs addressed by ADDRD ADDRA Input Read address bus A Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 301 Consult your synthesis tool documentation for details on RAM inference capabilities and coding examples. Xilinx suggests that you instantiate RAM32Ms if you have a need to implicitly specify the RAM function, or if you need to manually place or relationally place the component. If a synchronous read capability is desired, the RAM32M outputs can be connected to an FDRSE (FDCPE is asynchronous set/reset is necessary) in order to improve the output timing of the function.
Page 302 Unless they already exist, copy the following two statements and paste them before the entity declaration. Library UNISIM; use UNISIM.vcomponents.all; -- RAM32M: 32-deep by 8-wide Multi Port LUT RAM Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 RAM32M_inst : RAM32M generic map ( INIT_A => X"0000000000000000", -- Initial contents of A port INIT_B =>...
Page 303 // Write clock input .WE(WE) // Write enable input // End of RAM32M_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 304 1 (read) data_a data_d ↑ 1 (write) data_d ↓ 1 (read) data_a data_d Design Entry Method Instantiation Inference Recommended CORE Generator™ and wizards Macro support Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 305 UNISIM.vcomponents.all; -- RAM32X1D: 32 x 1 positive edge write, asynchronous read dual-port distributed RAM Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 RAM32X1D_inst : RAM32X1D generic map ( INIT => X"00000000") -- Initial contents of RAM port map ( DPO =>...
Page 306 // Write clock input .WE(WE) // Write enable input // End of RAM32X1D_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 307 CORE Generator™ and wizards Macro support Available Attributes Attribute Data Type Allowed Values Default Descriptions INIT Hexadecimal Any 32-Bit Value All zeros Specifies initial contents of the RAM. Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 308 .WCLK(WCLK), // Write clock input .WE(WE) // Write enable input // End of RAM32X1S_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 309 Recommended CORE Generator™ and wizards Macro support Available Attributes Attribute Data Type Allowed Values Default Descriptions INIT Hexadecimal Any 32-Bit Value Initializes RAMs, registers, and look-up tables. Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 310 .WCLK(WCLK), // Write clock input .WE(WE) // Write enable input // End of RAM32X1S_1_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 311 D1:D0 D1:D0 1 (write) ↓ 1 (read) Data Data = word addressed by bits A4:A0 Design Entry Method Instantiation Inference Recommended CORE Generator™ and wizards Macro support Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 312 .WCLK(WCLK), // Write clock input .WE(WE) // Write enable input // End of RAM32X2S_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 313 ADDRA) Input Write data inputs addressed by ADDRD (read output is addressed by ADDRB) Input Write data inputs addressed by ADDRD (read output is addressed by ADDRC) Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 314 Consult your synthesis tool documentation for details on RAM inference capabilities and coding examples. Xilinx suggests that you instantiate RAM64Ms if you have a need to implicitly specify the RAM function, or if you need to manually place or relationally place the component. If a synchronous read capability is desired, the RAM64M outputs can be connected to an FDRSE (FDCPE is asynchronous set/reset is necessary) in order to improve the output timing of the function.
Page 315 Unless they already exist, copy the following two statements and paste them before the entity declaration. Library UNISIM; use UNISIM.vcomponents.all; -- RAM64M: 64-deep by 4-wide Multi Port LUT RAM Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 RAM64M_inst : RAM64M generic map ( INIT_A => X"0000000000000000", -- Initial contents of A port INIT_B =>...
Page 316 // Write enable input .WCLK(WCLK) // Write clock input // End of RAM64M_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 317 1 (read) data_a data_d ↑ 1 (write) data_d ↓ 1 (read) data_a data_d data_a = word addressed by bits A5:A0 data_d = word addressed by bits DPRA5:DPRA0 Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 318 UNISIM.vcomponents.all; -- RAM64X1D: 64 x 1 negative edge write, asynchronous read dual-port distributed RAM Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 RAM64X1D_1_inst : RAM64X1D_1 generic map ( INIT => X"0000000000000000") -- Initial contents of RAM port map ( DPO =>...
Page 319 // Write clock input .WE(WE) // Write enable input // End of RAM64X1D_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 320 Data ↑ 1 (write) ↓ Data 1 (read) Data = word addressed by bits A5:A0 Design Entry Method Instantiation Inference Recommended CORE Generator™ and wizards Macro support Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 321 // Write clock input .WE(WE) // Write enable input // End of RAM64X1S_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 322 CORE Generator™ and wizards Macro support Available Attributes Attribute Data Type Allowed Values Default Description INIT Hexadecimal Any 64-Bit Value All zeros Initializes ROMs, RAMs, registers, and look-up tables. Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 323 // Write clock input .WE(WE) // Write enable input // End of RAM64X1S_1_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 324 Input Port A address input bus/Read address input bus. Input ADDRBWRADDR[13:0] Port B address input bus/Write address input bus. CLKARDCLK Input Port A clock input/Read clock input. Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 325 Synchronous output register set/reset to value indicated by SRVAL_B. RSTREGB sets/resets the output register when DO_REG=1. RSTREG_PRIORITY_B determines if this signal gets priority over REGCEB. Not used when RAM_MODE=SDP. Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 326 Applies to port A in TDP mode and up to 18 lower bits (including parity bits) in SDP mode. Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 327 This value must be 0 if the Port A is not used. Otherwise, it should be set to the desired port width. In SDP mode, this is the read width including parity bits. Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 328 VHDL Instantiation Template Unless they already exist, copy the following two statements and paste them before the entity declaration. Library UNISIM; use UNISIM.vcomponents.all; Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 329 Chapter 4: About Design Elements -- RAMB18E1: 18K-bit Configurable Synchronous Block RAM Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 RAMB18E1_inst : RAMB18E1 generic map ( -- Colision check: Values ("ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE") SIM_COLLISION_CHECK => "ALL", -- DOA_REG, DOB_REG: Optional output register (0 or 1) DOA_REG =>...
Page 330 DIBDI => DIBDI, -- 16-bit input: B port data/MSB data input DIPBDIP => DIPBDIP -- 2-bit input: B port parity/MSB parity input -- End of RAMB18E1_inst instantiation Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 331 Chapter 4: About Design Elements Verilog Instantiation Template // RAMB18E1: 18K-bit Configurable Synchronous Block RAM Virtex-6 // Xilinx HDL Libraries Guide, version 14.5 RAMB18E1 #( // Colision check: Values ("ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE") .SIM_COLLISION_CHECK("ALL"), // DOA_REG, DOB_REG: Optional output register (0 or 1) .DOA_REG(0),...
Page 332 // Port B Data: 16-bit (each) input: Port B data .DIBDI(DIBDI), // 16-bit input: B port data/MSB data input .DIPBDIP(DIPBDIP) // 2-bit input: B port parity/MSB parity input // End of RAMB18E1_inst instantiation Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 333 Chapter 4: About Design Elements For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 334 RAM. Error detection and correction circuitry can also be enabled to uncover and rectify possible memory corruption. Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 335 Port A output register clock enable input/Output register clock enable input (valid only when DO_REG=1). REGCEB Input Port B output register clock enable (valid only when DO_REG=1 and RAM_MODE=TDP). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 336 ONLY", "NONE", occurs: "WARNING_ONLY" • "ALL" - warning produced and affected outputs/memory location go unknown (X) • "WARNING_ONLY" - warning produced and affected outputs/memory retain last value Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 337 INITP_00 to Hexa- All zeros to all ones All zeros Allows specification of the initial INITP_0F decimal contents of the 4 kb parity data memory array. Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 338 • "READ_FIRST" - previous RAM contents for that memory location appear on the output port • "NO_CHANGE" - previous value on the output port remains the same. Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 339 Unless they already exist, copy the following two statements and paste them before the entity declaration. Library UNISIM; use UNISIM.vcomponents.all; -- RAMB36E1: 36K-bit Configurable Synchronous Block RAM Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 RAMB36E1_inst : RAMB36E1 generic map ( -- Colision check: Values ("ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE") SIM_COLLISION_CHECK => "ALL", -- DOA_REG, DOB_REG: Optional output register (0 or 1) DOA_REG =>...
Page 340 INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 341 -- Cascade Signals: 1-bit (each) output: BRAM cascade ports (to create 64kx1) CASCADEOUTA => CASCADEOUTA, -- 1-bit output: A port cascade output CASCADEOUTB => CASCADEOUTB, -- 1-bit output: B port cascade output Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 342 -- End of RAMB36E1_inst instantiation Verilog Instantiation Template // RAMB36E1: 36K-bit Configurable Synchronous Block RAM Virtex-6 // Xilinx HDL Libraries Guide, version 14.5 RAMB36E1 #( // Colision check: Values ("ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE") .SIM_COLLISION_CHECK("ALL"), // DOA_REG, DOB_REG: Optional output register (0 or 1) .DOA_REG(0),...
Page 343 .INIT_27(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_40(256’h0000000000000000000000000000000000000000000000000000000000000000), .INIT_41(256’h0000000000000000000000000000000000000000000000000000000000000000), Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 344 // RAM initialization // file // RAM_EXTENSION_A, RAM_EXTENSION_B: Selects cascade mode ("UPPER", "LOWER", or "NONE") .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), // "SDP" or "TDP" .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), // "PERFORMANCE" or // "DELAYED_WRITE" Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 345 // 4-bit input: B port parity/MSB parity input // End of RAMB36E1_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 346 A=FH to the least-significant digit A=0H. An error occurs if the INIT=value is not specified. Logic Table Input Output INIT(0) INIT(1) INIT(2) INIT(3) INIT(4) INIT(5) INIT(6) INIT(7) INIT(8) INIT(9) INIT(10) INIT(11) INIT(12) INIT(13) INIT(14) INIT(15) Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 347 Unless they already exist, copy the following two statements and paste them before the entity declaration. Library UNISIM; use UNISIM.vcomponents.all; -- ROM128X1: 128 x 1 Asynchronous Distributed (LUT) ROM Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 ROM128X1_inst : ROM128X1 generic map ( INIT => X"00000000000000000000000000000000") port map ( O =>...
Page 348 Chapter 4: About Design Elements For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 349 An error occurs if the INIT=value is not specified. Logic Table Input Output INIT(0) INIT(1) INIT(2) INIT(3) INIT(4) INIT(5) INIT(6) INIT(7) INIT(8) INIT(9) INIT(10) INIT(11) INIT(12) INIT(13) INIT(14) INIT(15) Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 350 Unless they already exist, copy the following two statements and paste them before the entity declaration. Library UNISIM; use UNISIM.vcomponents.all; -- ROM256X1: 256 x 1 Asynchronous Distributed (LUT) ROM Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 ROM256X1_inst : ROM256X1 generic map ( INIT => X"0000000000000000000000000000000000000000000000000000000000000000") port map ( O =>...
Page 351 Chapter 4: About Design Elements For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 352 An error occurs if the INIT=value is not specified. Logic Table Input Output INIT(0) INIT(1) INIT(2) INIT(3) INIT(4) INIT(5) INIT(6) INIT(7) INIT(8) INIT(9) INIT(10) INIT(11) INIT(12) INIT(13) INIT(14) INIT(15) Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 353 .A3(A3), // ROM address[3] .A4(A4) // ROM address[4] // End of ROM32X1_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 354 A=FH to the least-significant digit A=0H. An error occurs if the INIT=value is not specified. Logic Table Input Output INIT(0) INIT(1) INIT(2) INIT(3) INIT(4) INIT(5) INIT(6) INIT(7) INIT(8) INIT(9) INIT(10) INIT(11) INIT(12) INIT(13) INIT(14) INIT(15) Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 355 .A4(A4), // ROM address[4] .A5(A5) // ROM address[5] // End of ROM64X1_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 356 0 = CRC error • 1 = No CRC error When the SEU detection function is enabled, INIT_B is optionally driven Low when a read back CRC error is detected. Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 357 Macro support Xilinx suggests that you instantiate this in the testbench file and not an implementation file or file used during synthesis of the design. It may be used in conjunction with the design in order to help determine interaction and start-up sequences between configuration loading and device start-up.
Page 358 // End of SIM_CONFIG_V6_inst instantiation For More Information • See the Synthesis and Simulation Design Guide (UG626). • See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 359 When the SEU detection function is enabled, INIT_B is optionally driven Low when a read back CRC error is detected. Input Mode pins - determine configuration mode. PROGB Input Active-Low asynchronous full-chip reset. Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 360 Macro support Xilinx suggests that you instantiate this in the testbench file and not an implementation file or file used during synthesis of the design. It may be used in conjunction with the design in order to help determine interaction and start-up sequences between configuration loading and device start-up.
Page 361 // End of SIM_CONFIG_V6_SERIAL_inst instantiation For More Information • See the Synthesis and Simulation Design Guide (UG626). • See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 362 When CE is Low, the register ignores clock transitions. Logic Table Inputs Output Q(Am) ↑ Q(Am - 1) m= 0, 1, 2, 3 Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 363 Unless they already exist, copy the following two statements and paste them before the entity declaration. Library UNISIM; use UNISIM.vcomponents.all; -- SRL16E: 16-bit shift register LUT with clock enable operating on posedge of clock Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 SRL16E_inst : SRL16E generic map ( INIT => X"0000") port map ( Q =>...
Page 364 // Clock input .D(D) // SRL data input // End of SRL16E_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 365 Shift register data input Input Clock Input Active high clock enable Input Dynamic depth selection of the SRL A=00000 ==> 1-bit shift length A=11111 ==> 32-bit shift length Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 366 Unless they already exist, copy the following two statements and paste them before the entity declaration. Library UNISIM; use UNISIM.vcomponents.all; -- SRLC32E: 32-bit variable length shift register LUT with clock enable Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 SRLC32E_inst : SRLC32E generic map ( INIT => X"00000000") port map ( Q => Q, -- SRL data output Q31 =>...
Page 367 .CLK(CLK), // Clock input .D(D) // SRL data input // End of SRLC32E_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 368 This pin is an output into the FPGA fabric. It echoes the "end of startup" flag into the FPGA fabric. This pin can be used as a reset signal. Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 369 FPGA fabric. It enables the tristate nature of the FPGA’s DONE pin. Generally, this should be tied low. Tying this high will inhibit the assertion of DONE. Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 370 Unless they already exist, copy the following two statements and paste them before the entity declaration. Library UNISIM; use UNISIM.vcomponents.all; -- STARTUP_VIRTEX6: STARTUP Block Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 STARTUP_VIRTEX6_inst : STARTUP_VIRTEX6 generic map ( PROG_USR => FALSE -- Activate program event security feature. Requires encrypted bitstreams.
Page 371 // 1-bit input: User DONE 3-state enable output // End of STARTUP_VIRTEX6_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 372 1-bit output end of sequence JTAGBUSY Output 1-bit output JTAG DRP busy JTAGLOCKED Output 1-bit output DRP port lock JTAGMODIFIED Output 1-bit output JTAG write to DRP Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 373 16’h0000 to 16’h0000 Test register 0 decimal 16’hffff INIT_44 Hexa- Test register 1 16’h0000 to 16’h0000 decimal 16’hffff INIT_45 Hexa- Test register 2 16’h0000 to 16’h0000 decimal 16’hffff Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 374: Library Unisim; Use Unisim.vcomponents.all
VHDL Instantiation Template Unless they already exist, copy the following two statements and paste them before the entity declaration. Library UNISIM; use UNISIM.vcomponents.all; Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 375 Chapter 4: About Design Elements -- SYSMON: System Monitor Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 SYSMON_inst : SYSMON generic map ( -- INIT_40 - INIT_42: System Monitor configuration registers INIT_40 => X"0000", INIT_41 => X"0000", INIT_42 => X"0800", -- INIT_43 - INIT_47: System Monitor Test registers (do not edit) INIT_43 =>...
Page 376 Chapter 4: About Design Elements Verilog Instantiation Template // SYSMON: System Monitor Virtex-6 // Xilinx HDL Libraries Guide, version 14.5 SYSMON #( // INIT_40 - INIT_42: System Monitor configuration registers .INIT_40(16’h0000), .INIT_41(16’h0000), .INIT_42(16’h0800), // INIT_43 - INIT_47: System Monitor Test registers (do not edit) .INIT_43(16’h0000),...
Page 377 Chapter 4: About Design Elements // End of SYSMON_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...
Page 378 FPGA Embedded Tri-Mode Ethernet MAC. Because it encompasses SecureIP encrypted HDL, it is also used for functional and timing simulations. This primitive can be simplified for specific customer needs by using the CORE Generator™ tool to create Ethernet MAC wrappers. Virtex-6 Libraries Guide for HDL Designs www.xilinx.com UG623 (v 14.5) March 20, 2013...
Page 379 Chapter 4: About Design Elements Design Entry Method To instantiate this component, use the Embedded Development Kit (EDK) or an associated core containing the component. Xilinx does not recommend direct instantiation of this component. For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).
Page 380 Unless they already exist, copy the following two statements and paste them before the entity declaration. Library UNISIM; use UNISIM.vcomponents.all; -- USR_ACCESS_VIRTEX6: Configuration Data Access Virtex-6 -- Xilinx HDL Libraries Guide, version 14.5 USR_ACCESS_VIRTEX6_inst : USR_ACCESS_VIRTEX6 port map ( CFGCLK => CFGCLK, -- 1-bit output: Configuration Clock output DATA =>...
Page 381 // 1-bit output: Active high data valid output // End of USR_ACCESS_VIRTEX6_inst instantiation For More Information See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets). Virtex-6 Libraries Guide for HDL Designs UG623 (v 14.5) March 20, 2013 www.xilinx.com...