Xilinx Virtex-6 Manual page 246

Chapter 4: About Design Elements
Inputs
I5 I4
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
INIT = Binary equivalent of the hexadecimal number assigned to the INIT attribute
Port Description
Name Direction
LO Output
I0, I1, I2, I3, I4, I5 Input
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
246
I3 I2
0 1
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1
0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1
Width
1
1
www.xilinx.com
I1 I0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
Function
6/5-LUT output or internal CLB connection
LUT inputs
Yes
Recommended
No
No
Virtex-6 Libraries Guide for HDL Designs
Outputs
LO
INIT[39]
INIT[40]
INIT[41]
INIT[42]
INIT[43]
INIT[44]
INIT[45]
INIT[46]
INIT[47]
INIT[48]
INIT[49]
INIT[50]
INIT[51]
INIT[52]
INIT[53]
INIT[54]
INIT[55]
INIT[56]
INIT[57]
INIT[58]
INIT[59]
INIT[60]
INIT[61]
INIT[62]
INIT[63]
UG623 (v 14.5) March 20, 2013