Xilinx Virtex-6 Manual page 282

Chapter 4: About Design Elements
Available Attributes
Attribute Data Type
DDR_CLK_
String
EDGE
INIT Binary
SRTYPE String
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- ODDR: Output Double Data Rate Output Register with Set, Reset
-- and Clock Enable.
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
ODDR_inst : ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '0', -- Initial value for Q port ('1' or '0')
SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
port map (
Q => Q, -- 1-bit DDR output
C => C, -- 1-bit clock input
CE => CE, -- 1-bit clock enable input
D1 => D1, -- 1-bit data input (positive edge)
D2 => D2, -- 1-bit data input (negative edge)
R => R, -- 1-bit reset input
S => S -- 1-bit set input
);
-- End of ODDR_inst instantiation
Verilog Instantiation Template
// ODDR: Output Double Data Rate Output Register with Set, Reset
// and Clock Enable.
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
ODDR #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
.INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
) ODDR_inst (
.Q(Q), // 1-bit DDR output
.C(C), // 1-bit clock input
.CE(CE), // 1-bit clock enable input
.D1(D1), // 1-bit data input (positive edge)
.D2(D2), // 1-bit data input (negative edge)
.R(R), // 1-bit reset
.S(S) // 1-bit set
);
// End of ODDR_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
282
Allowed Values Default
"OPPOSITE_EDGE", "OPPOSITE_
"SAME_EDGE" EDGE"
0, 1 1
"SYNC", "ASYNC" "SYNC"
www.xilinx.com
Description
DDR clock mode recovery mode
selection.
Q initialization value.
Set/Reset type selection.
Sheets).
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013