Xilinx Virtex-6 Manual page 252

Chapter 4: About Design Elements
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- MMCM_ADV: Advanced Mixed Mode Clock Manager
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
MMCM_ADV_inst : MMCM_ADV
generic map (
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 5.0,
CLKFBOUT_PHASE => 0.0,
-- CLKIN_PERIOD: Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
CLKIN1_PERIOD => 0.0,
CLKIN2_PERIOD => 0.0,
CLKOUT0_DIVIDE_F => 1.0,
-- CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.01-0.99).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
CLKOUT6_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for CLKOUT outputs (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 0.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
CLKOUT6_PHASE => 0.0,
-- CLKOUT1_DIVIDE - CLKOUT6_DIVIDE: Divide amount for CLKOUT (1-128)
CLKOUT1_DIVIDE => 1,
CLKOUT2_DIVIDE => 1,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
CLKOUT6_DIVIDE => 1,
CLKOUT4_CASCADE => FALSE,
CLOCK_HOLD => FALSE,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 1,
-- REF_JITTER: Reference input jitter in UI (0.000-0.999).
REF_JITTER1 => 0.0,
REF_JITTER2 => 0.0,
STARTUP_WAIT => FALSE,
-- USE_FINE_PS: Fine phase shift enable (TRUE/FALSE)
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_USE_FINE_PS => FALSE,
CLKOUT2_USE_FINE_PS => FALSE,
CLKOUT3_USE_FINE_PS => FALSE,
CLKOUT4_USE_FINE_PS => FALSE,
CLKOUT5_USE_FINE_PS => FALSE,
CLKOUT6_USE_FINE_PS => FALSE
)
port map (
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
CLKOUT0 => CLKOUT0,
CLKOUT0B => CLKOUT0B,
CLKOUT1 => CLKOUT1,
CLKOUT1B => CLKOUT1B,
CLKOUT2 => CLKOUT2,
CLKOUT2B => CLKOUT2B,
CLKOUT3 => CLKOUT3,
CLKOUT3B => CLKOUT3B,
CLKOUT4 => CLKOUT4,
252
-- Jitter programming ("HIGH","LOW","OPTIMIZED")
-- Multiply value for all CLKOUT (5.0-64.0).
-- Phase offset in degrees of CLKFB (0.00-360.00).
-- Divide amount for CLKOUT0 (1.000-128.000).
-- Cascase CLKOUT4 counter with CLKOUT6 (TRUE/FALSE)
-- Hold VCO Frequency (TRUE/FALSE)
-- "ZHOLD", "INTERNAL", "EXTERNAL", "CASCADE" or "BUF_IN"
-- Master division value (1-80)
-- Not supported. Must be set to FALSE.
-- 1-bit output: CLKOUT0 output
-- 1-bit output: Inverted CLKOUT0 output
-- 1-bit output: CLKOUT1 output
-- 1-bit output: Inverted CLKOUT1 output
-- 1-bit output: CLKOUT2 output
-- 1-bit output: Inverted CLKOUT2 output
-- 1-bit output: CLKOUT3 output
-- 1-bit output: Inverted CLKOUT3 output
-- 1-bit output: CLKOUT4 output
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Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013