Xilinx Virtex-6 Manual page 103

CARRY4
Primitive: Fast Carry Logic with Look Ahead
Introduction
This circuit design represents the fast carry logic for a slice. The carry chain consists of a series of four MUXes
and four XORs that connect to the other logic (LUTs) in the slice via dedicated routes to form more complex
functions. The fast carry logic is useful for building arithmetic functions like adders, counters, subtractors and
add/subs, as well as such other logic functions as wide comparators, address decoders, and some logic gates
(specifically, AND and OR).
Port Descriptions
Port Direction
O Output
CO Output
DI Input
Input
S
CYINIT Input
CI Input
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Width Function
4
Carry chain XOR general data out
4
Carry-out of each stage of the carry chain
4
Carry-MUX data input
4
Carry-MUX select line
1
Carry-in initialization input
1
Carry cascade input
Yes
Recommended
No
No
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Chapter 4: About Design Elements
103