Xilinx Virtex-6 Manual page 371

Verilog Instantiation Template
// STARTUP_VIRTEX6: STARTUP Block
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
STARTUP_VIRTEX6 #(
.PROG_USR("FALSE") // Activate program event security feature. Requires encrypted bitstreams.
)
STARTUP_VIRTEX6_inst (
.CFGCLK(CFGCLK),
.CFGMCLK(CFGMCLK),
.DINSPI(DINSPI),
.EOS(EOS),
.PREQ(PREQ),
.TCKSPI(TCKSPI),
.CLK(CLK),
.GSR(GSR),
.GTS(GTS),
.KEYCLEARB(KEYCLEARB), // 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
.PACK(PACK),
.USRCCLKO(USRCCLKO),
.USRCCLKTS(USRCCLKTS), // 1-bit input: User CCLK 3-state enable input
.USRDONEO(USRDONEO),
.USRDONETS(USRDONETS)
);
// End of STARTUP_VIRTEX6_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
// 1-bit output: Configuration main clock output
// 1-bit output: Configuration internal oscillator clock output
// 1-bit output: DIN SPI PROM access output
// 1-bit output: Active high output signal indicating the End Of Configuration.
// 1-bit output: PROGRAM request to fabric output
// 1-bit output: TCK configuration pin access output
// 1-bit input: User start-up clock input
// 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
// 1-bit input: Global 3-state input (GTS cannot be used for the port name)
// 1-bit input: PROGRAM acknowledge input
// 1-bit input: User CCLK input
// 1-bit input: User DONE pin output control
// 1-bit input: User DONE 3-state enable output
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