Xilinx Virtex-6 Manual page 290

Chapter 4: About Design Elements
Introduction
This design element is intended for use in conjunction with other resources located in the FPGA, such as the
RocketIO™ transceivers, block RAMs, and various clocking resources. To implement an Endpoint, Root Port, or
custom PCI EXPRESS® design using PCIe_2_0, designers must use the CORE Generator™ software tool (part of
the ISE® Design Suite) to create a LogiCORE™ IP core for PCI EXPRESS designs. The LogiCORE instantiates
the PCIE_2_0 software primitive, connects the interfaces to the correct FPGA resources, sets all attributes, and
presents a simple, user-friendly interface.
Design Entry Method
To instantiate this component, use the PCI EXPRESS core or an associated core containing the component. Xilinx
does not recommend direct instantiation of this component.
For More Information
• See the Virtex-6 FPGA RocketIO GTX Transceivers User Guide
• See the Virtex-6 FPGA User Documentation (User Guides and Data
290
(UG366).
Sheets).
Virtex-6 Libraries Guide for HDL Designs
www.xilinx.com UG623 (v 14.5) March 20, 2013